Date: Wed, 22 Nov 2000 00:26:29 -0500 (EST) From: Daniel Eischen <eischen@vigrid.com> To: Arun Sharma <arun@sharmas.dhs.org> Cc: arch@FreeBSD.ORG Subject: Re: Thread-specific data and KSEs Message-ID: <Pine.SUN.3.91.1001122001113.7761B-100000@pcnet1.pcnet.com> In-Reply-To: <20001121200541.A21911@sharmas.dhs.org>
next in thread | previous in thread | raw e-mail | index | archive | help
On Tue, 21 Nov 2000, Arun Sharma wrote:
> On Tue, Nov 21, 2000 at 10:33:50PM -0500, Daniel Eischen wrote:
> > On Tue, 21 Nov 2000, Alfred Perlstein wrote:
> > > * Daniel Eischen <eischen@vigrid.com> [001121 19:15] wrote:
> > > > >
> > > > > Don't more segment registers cause more overhead for context switches?
> > > >
> > > > It's just one more register that has to be saved. I don't
> > > > think it's going to matter much.
> > >
> > > No extra TLB faults/invalidations? Aren't segment registers
> > > somewhat expensive to load?
> >
> > Not according to swtch.s, it's just a movl instruction. I don't
> > need to use the segment register to address anything. I just
> > need to load it with a value (an index into a global array
> > of per-KSE structures).
>
> Loading a segment register on x86 results in privilege level checking.
> It may even generate a general protection fault.
>
> Section 4.6 of vol 3 (system programming guide) from Intel
> has more details.
Any other ideas?
--
"Some folks are into open source, but me, I'm into open bar."
-- Spencer F. Katt
To Unsubscribe: send mail to majordomo@FreeBSD.org
with "unsubscribe freebsd-arch" in the body of the message
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?Pine.SUN.3.91.1001122001113.7761B-100000>