From owner-svn-src-all@freebsd.org Fri Jul 17 14:33:49 2015 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 3763D9A4D76; Fri, 17 Jul 2015 14:33:49 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 0B6A515A8; Fri, 17 Jul 2015 14:33:48 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.70]) by repo.freebsd.org (8.14.9/8.14.9) with ESMTP id t6HEXmtd024695; Fri, 17 Jul 2015 14:33:48 GMT (envelope-from zbb@FreeBSD.org) Received: (from zbb@localhost) by repo.freebsd.org (8.14.9/8.14.9/Submit) id t6HEXmlk024694; Fri, 17 Jul 2015 14:33:48 GMT (envelope-from zbb@FreeBSD.org) Message-Id: <201507171433.t6HEXmlk024694@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: zbb set sender to zbb@FreeBSD.org using -f From: Zbigniew Bodek Date: Fri, 17 Jul 2015 14:33:48 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r285655 - head/sys/arm64/arm64 X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 17 Jul 2015 14:33:49 -0000 Author: zbb Date: Fri Jul 17 14:33:47 2015 New Revision: 285655 URL: https://svnweb.freebsd.org/changeset/base/285655 Log: Fix possible coherency issues between PEs related to I-cache Basing on B.2.3.4: Synchronization and coherency issues between data and instruction accesses. To ensure that modified instructions are visible to all PEs (Processing Elements) in a shareability domain one need to perform following sequence: 1. Clean D-cache 2. Ensure the visibility of data cleaned from cache 3. Invalidate I-cache 4. Ensure completion 5. In SMP system PE must issue isb to ensure execution of the modified instructions Reviewed by: andrew Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3106 Modified: head/sys/arm64/arm64/cpufunc_asm.S Modified: head/sys/arm64/arm64/cpufunc_asm.S ============================================================================== --- head/sys/arm64/arm64/cpufunc_asm.S Fri Jul 17 14:08:08 2015 (r285654) +++ head/sys/arm64/arm64/cpufunc_asm.S Fri Jul 17 14:33:47 2015 (r285655) @@ -61,17 +61,18 @@ __FBSDID("$FreeBSD$"); add x1, x1, x2 /* Add these to the size */ bic x0, x0, x4 /* Clear the low bit of the address */ 1: + dc \dcop, x0 + dsb ish .if \ic != 0 ic \icop, x0 + dsb ish .endif - dc \dcop, x0 add x0, x0, x3 /* Move to the next line */ subs x1, x1, x3 /* Reduce the size */ b.hi 1b /* Check if we are done */ .if \ic != 0 isb .endif - dsb ish ret .endm