From nobody Fri Jul 7 19:25:03 2023 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4QyNdX2W6hz4lW4h; Fri, 7 Jul 2023 19:25:04 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4QyNdW6lRzz3qJ2; Fri, 7 Jul 2023 19:25:03 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1688757903; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=lonBKT7EGTUazlAOFE/g79knPONEyLHUu/Q2tBj4GMk=; b=OuvqQWdQH61F07tKPwYE0ffmXglgpVlFKhixu2FMqauGZLQCD6mLJH0xHgkC//jTj7W7Cx T8VvQ8yP65Zpbgd7orsP8J33f9NMO6fVAv0CSedC5UVFVxIQXthJCjlzzLas9qdALwyYd0 lZOKX3xnBbdc7KN5wo92RBz/A3ArqfqTvwtQuoMqwddHYFndk0mv493EtCsUb/bg3BbztW S7/PnBDqlvIAvSmuGUsOFy5wigdrzMj82FHN93PZGiTelIhI8GP4DhVLJlMT64y4vmXggI 7K2OpjBa4PJmQu8danQSAWyYx0oauX3r2xoQNNkrITz0898w00CY7uYm+gcBaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1688757903; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=lonBKT7EGTUazlAOFE/g79knPONEyLHUu/Q2tBj4GMk=; b=WFjkO1PKI4y2zVPAtuiCRJAyaiRw/mRqQJJbxRtpVGxYSZ2gX2XkYBxS2C5II8K/ElD4xt p94KjmK4NqUgRB/GVsE4xjH6KrcGzYl8UWN6CSB0G0r38d2UWbNAmu8D4OE4BxOSj+3qXj DOcYOsu1yCJmEtJ+44zRg4kMdLU3O4bUCSM2XFi2hKKU14/B1wcilN5jdxutd0q6AsF7AB jNZG8S29yLSbbDvyCpVBN/fePZTCqFIEM4AhYu8HeRIAIQlvyuFYitPmRZKwHH7D1KHi1S GUxFGK2GzzlHbOwQa5GdtagatEFpkXn2fR0QMkBpCI3lLvyy3mmsTaqPBe38mA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1688757903; a=rsa-sha256; cv=none; b=tbeHLIm+Jsk58E5c83JKG4RgIMUZNTB4EAvzzqBcMMnv6mqMQILA44Pa9oOsqbWVNvEMb1 +PpzH5ziZqk2pLeAuMookPsUQ2wOYWQ9TnnotWw+fsbJB/s4qPtticAUUv+aEmyR097X+g l314ucoOI+j2oI9QCPOyNSrE840qQKaj7sToEfzScZpLf0Qsex/u2jIacByjKJtIxkXYNp cK1xDimV70BIi/TrHPwmwL65AWDENLSTmj5wi2t3u6LwQkuJLCXvx3pPYno2/AXyC47Fb2 Lcw8ANnCm+rZFtzsBhzWU/r05zbYTNYZNy5urNRlVgWl1gOwqH/z/X+lhZLpoQ== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4QyNdW5pGVzrBB; Fri, 7 Jul 2023 19:25:03 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.17.1/8.17.1) with ESMTP id 367JP3j7062285; Fri, 7 Jul 2023 19:25:03 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.17.1/8.17.1/Submit) id 367JP3GT062284; Fri, 7 Jul 2023 19:25:03 GMT (envelope-from git) Date: Fri, 7 Jul 2023 19:25:03 GMT Message-Id: <202307071925.367JP3GT062284@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Mitchell Horne Subject: git: 7b1b44551ff9 - stable/13 - arm64/disassem.c: Add shifted register definitions with ror List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mhorne X-Git-Repository: src X-Git-Refname: refs/heads/stable/13 X-Git-Reftype: branch X-Git-Commit: 7b1b44551ff9bc71031a8faebf7c560427f67880 Auto-Submitted: auto-generated X-ThisMailContainsUnwantedMimeParts: N The branch stable/13 has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=7b1b44551ff9bc71031a8faebf7c560427f67880 commit 7b1b44551ff9bc71031a8faebf7c560427f67880 Author: Mykola Hohsadze AuthorDate: 2023-06-17 15:31:25 +0000 Commit: Mitchell Horne CommitDate: 2023-07-07 19:20:50 +0000 arm64/disassem.c: Add shifted register definitions with ror Add disassembly support for the following shifted register instructions: * mvn * orn * orr * and * ands * bic * bics * eon * eor * tst According to Arm64 documenation, operational pseuducode of shifted register instruction must return `UNDEFINED` if shift type is `RESERVED` ('11'). Hence, removed "rsv" from `shift_2` array and add "ror". In case of shift type is 3 and this type is `RESERVED`, we will return `undefined`. Reviewed by: mhorne MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D40386 (cherry picked from commit 9aef25d2686b9e7fb9cb700d63291338e8e30bb6) --- sys/arm64/arm64/disassem.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/sys/arm64/arm64/disassem.c b/sys/arm64/arm64/disassem.c index f1a4f9206c1b..5dc0bf5100ef 100644 --- a/sys/arm64/arm64/disassem.c +++ b/sys/arm64/arm64/disassem.c @@ -53,6 +53,7 @@ __FBSDID("$FreeBSD$"); #define OP_RT_SP (1UL << 8) /* Use sp for RT otherwise xzr */ #define OP_RN_SP (1UL << 9) /* Use sp for RN otherwise xzr */ #define OP_RM_SP (1UL << 10) /* Use sp for RM otherwise xzr */ +#define OP_SHIFT_ROR (1UL << 11) /* Use ror shift type */ static const char *w_reg[] = { "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", @@ -69,7 +70,7 @@ static const char *x_reg[] = { }; static const char *shift_2[] = { - "lsl", "lsr", "asr", "rsv" + "lsl", "lsr", "asr", "ror" }; /* @@ -232,6 +233,28 @@ static struct arm64_insn arm64_i[] = { TYPE_01, 0 }, /* negs shifted register */ { "subs", "SF(1)|1101011|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)", TYPE_01, 0 }, /* subs shifted register */ + { "mvn", "SF(1)|0101010|SHIFT(2)|1|RM(5)|IMM(6)|11111|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* mvn shifted register */ + { "orn", "SF(1)|0101010|SHIFT(2)|1|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* orn shifted register */ + { "mov", "SF(1)|0101010000|RM(5)|000000|11111|RD(5)", + TYPE_01, 0 }, /* mov register */ + { "orr", "SF(1)|0101010|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* orr shifted register */ + { "and", "SF(1)|0001010|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* and shifted register */ + { "tst", "SF(1)|1101010|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|11111", + TYPE_01, OP_SHIFT_ROR }, /* tst shifted register */ + { "ands", "SF(1)|1101010|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* ands shifted register */ + { "bic", "SF(1)|0001010|SHIFT(2)|1|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* bic shifted register */ + { "bics", "SF(1)|1101010|SHIFT(2)|1|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* bics shifted register */ + { "eon", "SF(1)|1001010|SHIFT(2)|1|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* eon shifted register */ + { "eor", "SF(1)|1001010|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* eor shifted register */ { NULL, NULL } }; @@ -420,6 +443,8 @@ disasm(const struct disasm_interface *di, vm_offset_t loc, int altfmt) int pre; /* Indicate if x31 register should be printed as sp or xzr */ int rm_sp, rt_sp, rd_sp, rn_sp; + /* Indicate if shift type ror is supported */ + bool has_shift_ror; /* Initialize defaults, all are 0 except SF indicating 64bit access */ shift = rd = rm = rn = imm = idx = option = amount = scale = 0; @@ -464,6 +489,8 @@ disasm(const struct disasm_interface *di, vm_offset_t loc, int altfmt) rd_sp = i_ptr->special_ops & OP_RD_SP; rn_sp = i_ptr->special_ops & OP_RN_SP; + has_shift_ror = i_ptr->special_ops & OP_SHIFT_ROR; + /* Print opcode by type */ switch (i_ptr->type) { case TYPE_01: @@ -479,6 +506,13 @@ disasm(const struct disasm_interface *di, vm_offset_t loc, int altfmt) rm_absent = arm64_disasm_read_token(i_ptr, insn, "RM", &rm); arm64_disasm_read_token(i_ptr, insn, "SHIFT", &shift); + /* + * if shift type is RESERVED for shifted register instruction, + * print undefined + */ + if (shift == 3 && !has_shift_ror) + goto undefined; + di->di_printf("%s\t", i_ptr->name); /*