From owner-svn-src-head@freebsd.org Sat Jul 28 17:21:37 2018 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id DEFB1105797D; Sat, 28 Jul 2018 17:21:36 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 9462D765B7; Sat, 28 Jul 2018 17:21:36 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 76BB41B4F; Sat, 28 Jul 2018 17:21:36 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w6SHLaYW034091; Sat, 28 Jul 2018 17:21:36 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w6SHLYfN034083; Sat, 28 Jul 2018 17:21:34 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201807281721.w6SHLYfN034083@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Sat, 28 Jul 2018 17:21:34 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r336834 - in head/sys/arm: arm include mv/armadaxp ti X-SVN-Group: head X-SVN-Commit-Author: andrew X-SVN-Commit-Paths: in head/sys/arm: arm include mv/armadaxp ti X-SVN-Commit-Revision: 336834 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 28 Jul 2018 17:21:37 -0000 Author: andrew Date: Sat Jul 28 17:21:34 2018 New Revision: 336834 URL: https://svnweb.freebsd.org/changeset/base/336834 Log: Use the cp15 functions to read cp15 registers rather than using assembly functions. The former are static inline functions so will compile to a single instruction. Modified: head/sys/arm/arm/cpufunc.c head/sys/arm/arm/cpufunc_asm.S head/sys/arm/arm/identcpu-v4.c head/sys/arm/arm/trap-v4.c head/sys/arm/include/cpufunc.h head/sys/arm/mv/armadaxp/armadaxp.c head/sys/arm/mv/armadaxp/armadaxp_mp.c head/sys/arm/ti/ti_cpuid.c Modified: head/sys/arm/arm/cpufunc.c ============================================================================== --- head/sys/arm/arm/cpufunc.c Sat Jul 28 16:56:46 2018 (r336833) +++ head/sys/arm/arm/cpufunc.c Sat Jul 28 17:21:34 2018 (r336834) @@ -284,10 +284,8 @@ get_cachetype_cp15(void) u_int multiplier; u_char type; - __asm __volatile("mrc p15, 0, %0, c0, c0, 1" - : "=r" (ctype)); - - cpuid = cpu_ident(); + ctype = cp15_ctr_get(); + cpuid = cp15_midr_get(); /* * ...and thus spake the ARM ARM: * @@ -388,7 +386,7 @@ get_cachetype_cp15(void) int set_cpufuncs(void) { - cputype = cpu_ident(); + cputype = cp15_midr_get(); cputype &= CPU_ID_CPU_MASK; #if defined(CPU_ARM9E) @@ -553,7 +551,7 @@ arm11x6_setup(void) uint32_t tmp, tmp2; uint32_t cpuid; - cpuid = cpu_ident(); + cpuid = cp15_midr_get(); auxctrl = 0; auxctrl_wax = ~0; Modified: head/sys/arm/arm/cpufunc_asm.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm.S Sat Jul 28 16:56:46 2018 (r336833) +++ head/sys/arm/arm/cpufunc_asm.S Sat Jul 28 17:21:34 2018 (r336834) @@ -62,35 +62,10 @@ END(cpufunc_nullop) * */ -ENTRY(cpu_ident) - mrc p15, 0, r0, c0, c0, 0 - RET -END(cpu_ident) - -ENTRY(cpu_get_control) - mrc CP15_SCTLR(r0) - RET -END(cpu_get_control) - -ENTRY(cpu_read_cache_config) - mrc p15, 0, r0, c0, c0, 1 - RET -END(cpu_read_cache_config) - -ENTRY(cpu_faultstatus) - mrc p15, 0, r0, c5, c0, 0 - RET -END(cpu_faultstatus) - -ENTRY(cpu_faultaddress) - mrc p15, 0, r0, c6, c0, 0 - RET -END(cpu_faultaddress) - /* * Generic functions to write the internal coprocessor registers * - * + * Currently these registers are * c1 - CPU Control * c3 - Domain Access Control Modified: head/sys/arm/arm/identcpu-v4.c ============================================================================== --- head/sys/arm/arm/identcpu-v4.c Sat Jul 28 16:56:46 2018 (r336833) +++ head/sys/arm/arm/identcpu-v4.c Sat Jul 28 17:21:34 2018 (r336834) @@ -279,8 +279,8 @@ identify_arm_cpu(void) u_int cpuid, ctrl; int i; - ctrl = cpu_get_control(); - cpuid = cpu_ident(); + ctrl = cp15_sctlr_get(); + cpuid = cp15_midr_get(); if (cpuid == 0) { printf("Processor failed probe - no CPU ID\n"); Modified: head/sys/arm/arm/trap-v4.c ============================================================================== --- head/sys/arm/arm/trap-v4.c Sat Jul 28 16:56:46 2018 (r336833) +++ head/sys/arm/arm/trap-v4.c Sat Jul 28 17:21:34 2018 (r336834) @@ -189,8 +189,8 @@ abort_handler(struct trapframe *tf, int type) return (prefetch_abort_handler(tf)); /* Grab FAR/FSR before enabling interrupts */ - far = cpu_faultaddress(); - fsr = cpu_faultstatus(); + far = cp15_dfar_get(); + fsr = cp15_dfsr_get(); #if 0 printf("data abort: fault address=%p (from pc=%p lr=%p)\n", (void*)far, (void*)tf->tf_pc, (void*)tf->tf_svc_lr); Modified: head/sys/arm/include/cpufunc.h ============================================================================== --- head/sys/arm/include/cpufunc.h Sat Jul 28 16:56:46 2018 (r336833) +++ head/sys/arm/include/cpufunc.h Sat Jul 28 17:21:34 2018 (r336834) @@ -208,12 +208,8 @@ int set_cpufuncs (void); #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ void cpufunc_nullop (void); -u_int cpu_ident (void); u_int cpufunc_control (u_int clear, u_int bic); void cpu_domains (u_int domains); -u_int cpu_faultstatus (void); -u_int cpu_faultaddress (void); -u_int cpu_get_control (void); u_int cpu_pfr (int); #if defined(CPU_ARM9E) Modified: head/sys/arm/mv/armadaxp/armadaxp.c ============================================================================== --- head/sys/arm/mv/armadaxp/armadaxp.c Sat Jul 28 16:56:46 2018 (r336833) +++ head/sys/arm/mv/armadaxp/armadaxp.c Sat Jul 28 17:21:34 2018 (r336834) @@ -35,8 +35,9 @@ __FBSDID("$FreeBSD$"); #include #include -#include #include +#include +#include #include #include @@ -142,7 +143,7 @@ get_tclk_armadaxp(void) { uint32_t cputype; - cputype = cpu_ident(); + cputype = cp15_midr_get(); cputype &= CPU_ID_CPU_MASK; if (cputype == CPU_ID_MV88SV584X_V7) Modified: head/sys/arm/mv/armadaxp/armadaxp_mp.c ============================================================================== --- head/sys/arm/mv/armadaxp/armadaxp_mp.c Sat Jul 28 16:56:46 2018 (r336833) +++ head/sys/arm/mv/armadaxp/armadaxp_mp.c Sat Jul 28 17:21:34 2018 (r336834) @@ -107,7 +107,7 @@ mv_axp_platform_mp_start_ap(platform_t plat) * Initialization procedure depends on core revision, * in this step CHIP ID is checked to choose proper procedure */ - cputype = cpu_ident(); + cputype = cp15_midr_get(); cputype &= CPU_ID_CPU_MASK; /* Modified: head/sys/arm/ti/ti_cpuid.c ============================================================================== --- head/sys/arm/ti/ti_cpuid.c Sat Jul 28 16:56:46 2018 (r336833) +++ head/sys/arm/ti/ti_cpuid.c Sat Jul 28 17:21:34 2018 (r336834) @@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$"); #include #include +#include #include #include #include @@ -124,7 +125,7 @@ omap4_get_revision(void) * the ARM cpuid to get the correct revision. */ if (revision == 0) { - id_code = cpu_ident(); + id_code = cp15_midr_get(); revision = (id_code & 0xf) - 1; }