Date: Thu, 14 Dec 2000 07:58:11 -0600 (CST) From: Mike Meyer <mwm@mired.org> To: kstewart@urx.com Cc: questions@freebsd.org Subject: Re: advice with old equipment. Message-ID: <14904.53747.735579.713279@guru.mired.org> In-Reply-To: <3A38AAEE.56303833@urx.com> References: <14904.1150.593498.981432@guru.mired.org> <3A381379.9F464204@urx.com> <14904.20712.193427.889148@guru.mired.org> <3A3862E1.A0D6E0C2@urx.com> <14904.28164.273218.788343@guru.mired.org> <3A38AAEE.56303833@urx.com>
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Kent Stewart <kstewart@urx.com> types: > > > At some point after that, the cpu was spending time waiting for data > > > and cache would really become important for some types of > > > computations. On my systems currently, it is a 1/2 speed, full size > > > cache on the P-II's/III's and a 1/4 size, full speed cache on the > > > Celeron 433a. I had a 300a that I overclocked to 450 until it > > > died. For about 2 months it out performed a P-III 450. It died from > > > overheating building XFree86 3.3.4 after one of the releases. A > > > trivia point is that adding PC-100 memory to the Celeron's speeded > > > them up about 15%. You can get back some of the 150% you lose > > > because of the cache and FSB. > > I thought the PIIIs had full speed caches. > Only the Coppermines (?). They went to full speed cache when they > dropped the cache to 1/2 size. Before that they were 1/2 speed just > like the P-II's. Ah, ok. That makes sense. I suspect that means that 1/2 the cache at full speed is better for most applications than the full cache at 1/2 speed. > > > I got interested in the AMD Athlon because of the additional pipelines > > > that the Intel Pentium's didn't have. I thought pipelines were > > > important on the old Cray and a good algorithim would help the PC. > > Pipelines were important on the old Crays. However, the important > > pipline was in the array processors, not the CPU. When they did array > > operations, the data from the input arrays were pipelined through the > > array processor so that you could do hundreds of flops at the rate of > > one per machine cycle. The CPU was pretty much RISC, which made all > > the instruction decode stuff fast. For something like an AMD, the work > > that led to the MIPS (IIRC, that's a machine *without* Interlock > > Pipeline Stages - the compiler was supposed to make sure the there > > were no bubbles in the pipeline, so the hardware didn't have to, and > > hence could run faster) might be more relevant. > Ok, they got into that a little bit when you would attend one of their > performance courses. The first morning was all spent on understanding > your hardware. You really couldn't take advantage of the compiler and > the multiple cpu's until you understood some of those interactions but > they couldn't spend too much time on the hardware because someone else > was hired to cover that part. This is missing in the compilers we use. Who is "they" in this case? MIPS or Cray? The classes I took at Cray didn't run into that kind of problem. > Cray compilers with everything turned on were really slow. In 1988, I > think Lehey Fortran on a 486 25Mhz was just about the same speed on a > line count basis. From my benchmarks on the Cray I ran in the late 80s, it wouldn't surprise me if *most* character-oriented things were about the same speed on a 25MHz 486. The Cray architecture made doing a "grep" *slow* (fetch word, shift, mask, shift again, cmp to do a single byte compare). It wasn't noticably faster than a VAX for such things, and VAXen weren't particularly fast. On the other hand, if you set up your fortran to do array stuff - well, mflops was what the machine was known for. <mike -- Mike Meyer <mwm@mired.org> http://www.mired.org/home/mwm/ Independent WWW/Unix/FreeBSD consultant, email for more information. To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-questions" in the body of the message
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