From owner-dev-commits-src-branches@freebsd.org Wed Apr 21 07:59:41 2021 Return-Path: Delivered-To: dev-commits-src-branches@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id B250F5FB68B; Wed, 21 Apr 2021 07:59:41 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4FQCd94kfgz4mCj; Wed, 21 Apr 2021 07:59:41 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 953CE2298B; Wed, 21 Apr 2021 07:59:41 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 13L7xfha019407; Wed, 21 Apr 2021 07:59:41 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 13L7xf4h019406; Wed, 21 Apr 2021 07:59:41 GMT (envelope-from git) Date: Wed, 21 Apr 2021 07:59:41 GMT Message-Id: <202104210759.13L7xf4h019406@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Mateusz Piotrowski <0mp@FreeBSD.org> Subject: git: bd2cb05d2490 - stable/12 - spigen.4: Fix typos MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: 0mp X-Git-Repository: src X-Git-Refname: refs/heads/stable/12 X-Git-Reftype: branch X-Git-Commit: bd2cb05d24907e37029f252086aaef70d91c92ff Auto-Submitted: auto-generated X-BeenThere: dev-commits-src-branches@freebsd.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Commits to the stable branches of the FreeBSD src repository List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Apr 2021 07:59:41 -0000 The branch stable/12 has been updated by 0mp (doc, ports committer): URL: https://cgit.FreeBSD.org/src/commit/?id=bd2cb05d24907e37029f252086aaef70d91c92ff commit bd2cb05d24907e37029f252086aaef70d91c92ff Author: Mateusz Piotrowski <0mp@FreeBSD.org> AuthorDate: 2021-04-18 07:45:18 +0000 Commit: Mateusz Piotrowski <0mp@FreeBSD.org> CommitDate: 2021-04-21 07:58:37 +0000 spigen.4: Fix typos MFC after: 3 days (cherry picked from commit 40277af7f23405c276edf02c3ddc8e770a06e3f6) --- share/man/man4/spigen.4 | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/share/man/man4/spigen.4 b/share/man/man4/spigen.4 index f79bb85dcfaf..061c192ab572 100644 --- a/share/man/man4/spigen.4 +++ b/share/man/man4/spigen.4 @@ -57,8 +57,8 @@ device is associated with a single chip-select line on the bus, and all I/O performed through that instance is done with that chip-select line asserted. .Pp -SPI data transfers are inherently bi-directional; there are not separate -read and write operations. +SPI data transfers are inherently bi-directional; there are no separate +read and write operations. When commands and data are sent to a device, data also comes back from the device, although in some cases the data may not be useful (or even documented or predictable for some devices). @@ -117,7 +117,7 @@ Set the maximum clock speed (bus frequency in Hertz) to be used when communicating with this slave device. The setting remains in effect for subsequent transfers; it is not necessary to reset this before each transfer. -The actual bus frequency may be lower due to hardware limitiations +The actual bus frequency may be lower due to hardware limitations of the SPI bus controller device. .It Dv SPIGENIOC_GET_SPI_MODE Pq Vt uint32_t Get the SPI mode (clock polarity and phase) to be used