Date: Fri, 8 Dec 2000 20:55:44 +0000 (GMT) From: Terry Lambert <tlambert@primenet.com> To: msmith@FreeBSD.ORG (Mike Smith) Cc: smp@FreeBSD.ORG Subject: Re: Netgraph and SMP Message-ID: <200012082055.NAA22567@usr01.primenet.com> In-Reply-To: <200012080542.eB85gVN00523@mass.osd.bsdi.com> from "Mike Smith" at Dec 07, 2000 09:42:31 PM
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> > Er, what are you smoking Terry? You never 'update' the cache on another > > processor; the other processor snoops your cache/memory activity and > > invalidates its own cache based on your broadcasts. > > I should have added "if you're lucky" to this. Some platforms don't even > go that far. The BeBox is an example of a box without an L2 cachem and using the L2 cache control lines in order to implement MEI coherency for a maximum of two CPUs. You can actually get zero cycle bus arbitration to work with multiple MIPS processors (Phil Neiswanger initiated some work on this; I helped with the arbitration algorithm), also giving MEI coherency. I understand the limitations; please see my other posting. Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers. To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-smp" in the body of the message
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