Date: Fri, 29 Nov 1996 08:46:59 -0800 From: Erich Boleyn <erich@uruk.org> To: Peter Wemm <peter@spinner.dialix.com>, Nate Williams <nate@mt.sri.com> Cc: Steve Passe <smp@csn.net>, freebsd-smp@freebsd.org Subject: Pentium CPU steppings Message-ID: <E0vTW5b-000543-00@uruk.org> In-Reply-To: Your message of "Fri, 29 Nov 1996 12:21:04 %2B0800." <199611290421.MAA10484@spinner.DIALix.COM>
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Peter Wemm <peter@spinner.dialix.com> writes: > Nate Williams wrote: > > > > Processors: APIC ID Version State Family Model Step Fla > gs > > > > 0 0x11 BSP, usable 5 2 1 0x > 07bf > > > > 1 0x11 AP, usable 5 2 1 0x > 07bf > > > > ^^^ > > > > without problems (that I'm aware of). > > > > > > I think Step 6 was where they fixed the FPU divide bug.. (I saw a > > > reference to this on "The Ultimate Chip list" or something like that) > > > > Nope, I've got a Stepping 5 P100 chip here and it's work fine (been > > tested and everything). > > Well, that's what I suspected too. I had only seen step 1, 5 and much > higher. I wondered if there was a mistake in the list and in fact it was > step 5 that fixes it. (I have P5-90 Step 1 cpus btw) Uh... you can't just look at the "step" number. The "model" number is also quite relevant. The "family" is the chip design (386, 486, Pentium, etc.), the "model" is the major revision, and the "step" is the stepping. The 3 numbers are pretty much strictly ordered for severity of changes. The fdiv bug occurs in model 1 chips with stepping less then 6 (I think, don't quote me). A higher stepping in the same model, or any higher model with any stepping is fixed. -- Erich Stefan Boleyn \_ E-mail (preferred): <erich@uruk.org> Mad Genius wanna-be, CyberMuffin \__ (finger me for other stats) Web: http://www.uruk.org/~erich/ Motto: "I'll live forever or die trying"
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