From owner-svn-src-head@freebsd.org Mon Apr 23 12:23:06 2018 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 2E5EDFB7CCA; Mon, 23 Apr 2018 12:23:06 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id D4C8D6DF9C; Mon, 23 Apr 2018 12:23:05 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id CF955243DD; Mon, 23 Apr 2018 12:23:05 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w3NCN5lr061421; Mon, 23 Apr 2018 12:23:05 GMT (envelope-from br@FreeBSD.org) Received: (from br@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w3NCN527061419; Mon, 23 Apr 2018 12:23:05 GMT (envelope-from br@FreeBSD.org) Message-Id: <201804231223.w3NCN527061419@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: br set sender to br@FreeBSD.org using -f From: Ruslan Bukin Date: Mon, 23 Apr 2018 12:23:05 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r332887 - in head/sys: arm/conf dts/arm X-SVN-Group: head X-SVN-Commit-Author: br X-SVN-Commit-Paths: in head/sys: arm/conf dts/arm X-SVN-Commit-Revision: 332887 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Apr 2018 12:23:06 -0000 Author: br Date: Mon Apr 23 12:23:05 2018 New Revision: 332887 URL: https://svnweb.freebsd.org/changeset/base/332887 Log: Enable ARM PL330 DMA engine and Cadence Quad SPI flash controller on Intel Arria 10 SoC boards. Tested on Intel Arria 10 SoC Development Kit. Sponsored by: DARPA, AFRL Modified: head/sys/arm/conf/SOCFPGA head/sys/dts/arm/socfpga_arria10_socdk_sdmmc.dts Modified: head/sys/arm/conf/SOCFPGA ============================================================================== --- head/sys/arm/conf/SOCFPGA Mon Apr 23 12:20:07 2018 (r332886) +++ head/sys/arm/conf/SOCFPGA Mon Apr 23 12:23:05 2018 (r332887) @@ -47,6 +47,10 @@ options INTRNG # ARM MPCore timer device mpcore_timer +# DMA support +device xdma +device pl330 + # MMC/SD/SDIO Card slot support device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards @@ -80,6 +84,8 @@ device iicbus # SPI device spibus +device cqspi +device n25q # Ethernet device ether Modified: head/sys/dts/arm/socfpga_arria10_socdk_sdmmc.dts ============================================================================== --- head/sys/dts/arm/socfpga_arria10_socdk_sdmmc.dts Mon Apr 23 12:20:07 2018 (r332886) +++ head/sys/dts/arm/socfpga_arria10_socdk_sdmmc.dts Mon Apr 23 12:23:05 2018 (r332887) @@ -84,3 +84,37 @@ &usb0 { dr_mode = "host"; }; + +&qspi { + status = "okay"; + + dmas = <&pdma 24>, <&pdma 25>; + dma-names = "tx", "rx"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00aa"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@qspi-boot { + label = "boot"; + reg = <0x0 0x2720000>; + }; + + partition@qspi-rootfs { + label = "rootfs"; + reg = <0x2720000 0x58E0000>; + }; + }; +};