From owner-svn-src-head@freebsd.org Thu Sep 1 21:20:08 2016 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id F1FC8BCB3DE; Thu, 1 Sep 2016 21:20:08 +0000 (UTC) (envelope-from jmcneill@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id B6E45EAA; Thu, 1 Sep 2016 21:20:08 +0000 (UTC) (envelope-from jmcneill@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u81LK7GP063317; Thu, 1 Sep 2016 21:20:07 GMT (envelope-from jmcneill@FreeBSD.org) Received: (from jmcneill@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u81LK7rN063316; Thu, 1 Sep 2016 21:20:07 GMT (envelope-from jmcneill@FreeBSD.org) Message-Id: <201609012120.u81LK7rN063316@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jmcneill set sender to jmcneill@FreeBSD.org using -f From: Jared McNeill Date: Thu, 1 Sep 2016 21:20:07 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r305247 - head/sys/arm/allwinner/clk X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Sep 2016 21:20:09 -0000 Author: jmcneill Date: Thu Sep 1 21:20:07 2016 New Revision: 305247 URL: https://svnweb.freebsd.org/changeset/base/305247 Log: Add support for changing A23 PLL1 frequency. Modified: head/sys/arm/allwinner/clk/aw_pll.c Modified: head/sys/arm/allwinner/clk/aw_pll.c ============================================================================== --- head/sys/arm/allwinner/clk/aw_pll.c Thu Sep 1 21:19:11 2016 (r305246) +++ head/sys/arm/allwinner/clk/aw_pll.c Thu Sep 1 21:20:07 2016 (r305247) @@ -110,14 +110,14 @@ __FBSDID("$FreeBSD$"); #define A13_PLL2_PRE_DIV (0x1f << 0) #define A13_PLL2_PRE_DIV_SHIFT 0 +#define A23_PLL1_FACTOR_P (0x3 << 16) +#define A23_PLL1_FACTOR_P_SHIFT 16 #define A23_PLL1_FACTOR_N (0x1f << 8) #define A23_PLL1_FACTOR_N_SHIFT 8 #define A23_PLL1_FACTOR_K (0x3 << 4) #define A23_PLL1_FACTOR_K_SHIFT 4 #define A23_PLL1_FACTOR_M (0x3 << 0) #define A23_PLL1_FACTOR_M_SHIFT 0 -#define A23_PLL1_FACTOR_P (0x3 << 16) -#define A23_PLL1_FACTOR_P_SHIFT 16 #define A31_PLL1_LOCK (1 << 28) #define A31_PLL1_CPU_SIGMA_DELTA_EN (1 << 24) @@ -171,6 +171,24 @@ __FBSDID("$FreeBSD$"); #define CLKID_A31_PLL6 0 #define CLKID_A31_PLL6_X2 1 +struct aw_pll_factor { + unsigned int n; + unsigned int k; + unsigned int m; + unsigned int p; + uint64_t freq; +}; +#define PLLFACTOR(_n, _k, _m, _p, _freq) \ + { .n = (_n), .k = (_k), .m = (_m), .p = (_p), .freq = (_freq) } + +static struct aw_pll_factor aw_a23_pll1_factors[] = { + PLLFACTOR(16, 0, 0, 0, 408000000), + PLLFACTOR(26, 0, 0, 0, 648000000), + PLLFACTOR(16, 1, 0, 0, 816000000), + PLLFACTOR(20, 1, 0, 0, 1008000000), + PLLFACTOR(24, 1, 0, 0, 1200000000), +}; + enum aw_pll_type { AWPLL_A10_PLL1 = 1, AWPLL_A10_PLL2, @@ -557,6 +575,39 @@ a13_pll2_set_freq(struct aw_pll_sc *sc, } static int +a23_pll1_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout, + int flags) +{ + struct aw_pll_factor *f; + uint32_t val; + int n; + + f = NULL; + for (n = 0; n < nitems(aw_a23_pll1_factors); n++) { + if (aw_a23_pll1_factors[n].freq == *fout) { + f = &aw_a23_pll1_factors[n]; + break; + } + } + if (f == NULL) + return (EINVAL); + + DEVICE_LOCK(sc); + PLL_READ(sc, &val); + val &= ~(A23_PLL1_FACTOR_N|A23_PLL1_FACTOR_K|A23_PLL1_FACTOR_M| + A23_PLL1_FACTOR_P); + val |= (f->n << A23_PLL1_FACTOR_N_SHIFT); + val |= (f->k << A23_PLL1_FACTOR_K_SHIFT); + val |= (f->m << A23_PLL1_FACTOR_M_SHIFT); + val |= (f->p << A23_PLL1_FACTOR_P_SHIFT); + PLL_WRITE(sc, val); + DEVICE_UNLOCK(sc); + + return (0); + +} + +static int a23_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq) { uint32_t val, m, n, k, p; @@ -719,7 +770,7 @@ static struct aw_pll_funcs aw_pll_func[] PLL(AWPLL_A10_PLL5, a10_pll5_recalc, NULL, NULL), PLL(AWPLL_A10_PLL6, a10_pll6_recalc, a10_pll6_set_freq, a10_pll6_init), PLL(AWPLL_A13_PLL2, a13_pll2_recalc, a13_pll2_set_freq, NULL), - PLL(AWPLL_A23_PLL1, a23_pll1_recalc, NULL, NULL), + PLL(AWPLL_A23_PLL1, a23_pll1_recalc, a23_pll1_set_freq, NULL), PLL(AWPLL_A31_PLL1, a31_pll1_recalc, NULL, NULL), PLL(AWPLL_A31_PLL6, a31_pll6_recalc, NULL, a31_pll6_init), PLL(AWPLL_A80_PLL4, a80_pll4_recalc, NULL, NULL),