From owner-svn-soc-all@FreeBSD.ORG Mon Jun 18 12:33:40 2012 Return-Path: Delivered-To: svn-soc-all@FreeBSD.org Received: from socsvn.FreeBSD.org (unknown [IPv6:2001:4f8:fff6::2f]) by hub.freebsd.org (Postfix) with SMTP id 774BE1065673 for ; Mon, 18 Jun 2012 12:33:38 +0000 (UTC) (envelope-from aleek@FreeBSD.org) Received: by socsvn.FreeBSD.org (sSMTP sendmail emulation); Mon, 18 Jun 2012 12:33:38 +0000 Date: Mon, 18 Jun 2012 12:33:38 +0000 From: aleek@FreeBSD.org To: svn-soc-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-Id: <20120618123338.774BE1065673@hub.freebsd.org> Cc: Subject: socsvn commit: r237889 - in soc2012/aleek/beaglexm-armv6/sys: arm/ti/am37x boot/fdt/dts X-BeenThere: svn-soc-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the entire Summer of Code repository List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jun 2012 12:33:40 -0000 Author: aleek Date: Mon Jun 18 12:33:37 2012 New Revision: 237889 URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=237889 Log: stub of PRCM driver Modified: soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_prcm.c soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts Modified: soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_prcm.c ============================================================================== --- soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_prcm.c Mon Jun 18 11:49:23 2012 (r237888) +++ soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_prcm.c Mon Jun 18 12:33:37 2012 (r237889) @@ -1,7 +1,10 @@ /*- - * Copyright (c) 2012 Damjan Marion + * Copyright (c) 2011 + * Ben Gray . * All rights reserved. * + * Modified 2012 Aleksander Dutkowski + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -11,10 +14,10 @@ * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) @@ -29,103 +32,146 @@ #include #include -#include #include #include -#include +#include +#include #include -#include -#include -#include +#include +#include + #include #include +#include #include +#include #include #include -#include #include +#include -#include -#include -#include -#include -#include -#include -#define CM_PER 0 -#define CM_PER_L4LS_CLKSTCTRL (CM_PER + 0x000) -#define CM_PER_L3S_CLKSTCTRL (CM_PER + 0x004) -#define CM_PER_L3_CLKSTCTRL (CM_PER + 0x00C) -#define CM_PER_CPGMAC0_CLKCTRL (CM_PER + 0x014) -#define CM_PER_USB0_CLKCTRL (CM_PER + 0x01C) -#define CM_PER_TPTC0_CLKCTRL (CM_PER + 0x024) -#define CM_PER_MMC0_CLKCTRL (CM_PER + 0x03C) -#define CM_PER_I2C2_CLKCTRL (CM_PER + 0x044) -#define CM_PER_I2C1_CLKCTRL (CM_PER + 0x048) -#define CM_PER_TIMER7_CLKCTRL (CM_PER + 0x07C) -#define CM_PER_TIMER2_CLKCTRL (CM_PER + 0x080) -#define CM_PER_TIMER3_CLKCTRL (CM_PER + 0x084) -#define CM_PER_TIMER4_CLKCTRL (CM_PER + 0x088) -#define CM_PER_GPIO1_CLKCTRL (CM_PER + 0x0AC) -#define CM_PER_GPIO2_CLKCTRL (CM_PER + 0x0B0) -#define CM_PER_GPIO3_CLKCTRL (CM_PER + 0x0B4) -#define CM_PER_TPCC_CLKCTRL (CM_PER + 0x0BC) -#define CM_PER_L3_INSTR_CLKCTRL (CM_PER + 0x0DC) -#define CM_PER_L3_CLKCTRL (CM_PER + 0x0E0) -#define CM_PER_TIMER5_CLKCTRL (CM_PER + 0x0EC) -#define CM_PER_TIMER6_CLKCTRL (CM_PER + 0x0F0) -#define CM_PER_MMC1_CLKCTRL (CM_PER + 0x0F4) -#define CM_PER_MMC2_CLKCTRL (CM_PER + 0x0F8) -#define CM_PER_TPTC1_CLKCTRL (CM_PER + 0x0FC) -#define CM_PER_TPTC2_CLKCTRL (CM_PER + 0x100) -#define CM_PER_OCPWP_L3_CLKSTCTRL (CM_PER + 0x12C) -#define CM_PER_OCPWP_CLKCTRL (CM_PER + 0x130) -#define CM_PER_CPSW_CLKSTCTRL (CM_PER + 0x144) - -#define CM_WKUP 0x400 -#define CM_WKUP_CLKSTCTRL (CM_WKUP + 0x000) -#define CM_WKUP_CONTROL_CLKCTRL (CM_WKUP + 0x004) -#define CM_WKUP_GPIO0_CLKCTRL (CM_WKUP + 0x008) -#define CM_WKUP_CM_L3_AON_CLKSTCTRL (CM_WKUP + 0x01C) -#define CM_WKUP_CM_CLKSEL_DPLL_MPU (CM_WKUP + 0x02C) -#define CM_WKUP_CM_CLKDCOLDO_DPLL_PER (CM_WKUP + 0x07C) -#define CM_WKUP_I2C0_CLKCTRL (CM_WKUP + 0x0B8) - -#define CM_DPLL 0x500 -#define CLKSEL_TIMER7_CLK (CM_DPLL + 0x004) -#define CLKSEL_TIMER2_CLK (CM_DPLL + 0x008) -#define CLKSEL_TIMER3_CLK (CM_DPLL + 0x00C) -#define CLKSEL_TIMER4_CLK (CM_DPLL + 0x010) -#define CLKSEL_TIMER5_CLK (CM_DPLL + 0x018) -#define CLKSEL_TIMER6_CLK (CM_DPLL + 0x01C) +/* + * This file defines the clock configuration for the OMAP3xxx series of + * devices. + * + * How This is Suppose to Work + * =========================== + * - There is a top level omap_prcm module that defines all OMAP SoC drivers + * should use to enable/disable the system clocks regardless of the version + * of OMAP device they are running on. This top level PRCM module is just + * a thin shim to chip specific functions that perform the donkey work of + * configuring the clock - this file is the 'donkey' for OMAP35xx devices. + * + * - The key bit in this file is the omap_clk_devmap array, it's + * used by the omap_prcm driver to determine what clocks are valid and which + * functions to call to manipulate them. + * + * - In essence you just need to define some callbacks for each of the + * clocks and then you're done. + * + * - The other thing worth noting is that when the omap_prcm device + * is registered you typically pass in some memory ranges which are the + * SYS_MEMORY resources. These resources are in turn allocated using + * bus_allocate_resources(...) and the resource handles are passed to all + * individual clock callback handlers. + * + * + * + * + */ + + +void +omap3_clk_init(device_t dev, int prio); + +#define FREQ_96MHZ 96000000 +#define FREQ_64MHZ 64000000 +#define FREQ_48MHZ 48000000 +#define FREQ_32KHZ 32000 + + + +/** + * Only one memory regions is needed for OMAP35xx clock control (unlike OMAP4) + * + * CM Instance - 0x4800 4000 : 0x4800 5500 + * PRM Instance - 0x4830 6000 : 0x4830 8000 + * + */ +//#define CM_INSTANCE_MEM_REGION 0 +//#define PRM_INSTANCE_MEM_REGION 1 -#define PRM_DEVICE_OFFSET 0xF00 -#define PRM_RSTCTRL (PRM_DEVICE_OFFSET + 0x00) +#define IVA2_CM_OFFSET 0x0000 +#define OCP_SYSTEM_CM_OFFSET 0x0800 +#define MPU_CM_OFFSET 0x0900 +#define CORE_CM_OFFSET 0x0A00 +#define SGX_CM_OFFSET 0x0B00 +#define WKUP_CM_OFFSET 0x0C00 +#define CLOCK_CTRL_CM_OFFSET 0x0D00 +#define DSS_CM_OFFSET 0x0E00 +#define CAM_CM_OFFSET 0x0F00 +#define PER_CM_OFFSET 0x1000 +#define EMU_CM_OFFSET 0x1100 +#define GLOBAL_CM_OFFSET 0x1200 +#define NEON_CM_OFFSET 0x1300 +#define USBHOST_CM_OFFSET 0x1400 + +#define IVA2_PRM_OFFSET 0x0000 +#define OCP_SYSTEM_PRM_OFFSET 0x0800 +#define MPU_PRM_OFFSET 0x0900 +#define CORE_PRM_OFFSET 0x0A00 +#define SGX_PRM_OFFSET 0x0B00 +#define WKUP_PRM_OFFSET 0x0C00 +#define CLOCK_CTRL_PRM_OFFSET 0x0D00 +#define DSS_PRM_OFFSET 0x0E00 +#define CAM_PRM_OFFSET 0x0F00 +#define PER_PRM_OFFSET 0x1000 +#define EMU_PRM_OFFSET 0x1100 +#define GLOBAL_PRM_OFFSET 0x1200 +#define NEON_PRM_OFFSET 0x1300 +#define USBHOST_PRM_OFFSET 0x1400 struct omap3_prcm_softc { - struct resource * res[2]; - bus_space_tag_t bst; - bus_space_handle_t bsh; + struct resource *res[2]; + bus_space_tag_t prm_bst, cm_bst; + bus_space_tag_t prm_bsh, cm_bsh; }; static struct resource_spec omap3_prcm_spec[] = { - { SYS_RES_MEMORY, 0, RF_ACTIVE }, - { -1, 0 } + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL }, + { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL }, + { SYS_RES_MEMORY, 3, RF_ACTIVE | RF_OPTIONAL }, + { -1, 0, 0 } }; -static struct omap3_prcm_softc *omap3_prcm_sc = NULL; +static int +omap3_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); + +static int +omap3_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); + +static int +omap3_clk_generic_activate(struct ti_clock_dev *clkdev); + +static int +omap3_clk_generic_deactivate(struct ti_clock_dev *clkdev); + +static int +omap3_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); + +static int +omap3_clk_generic_accessible(struct ti_clock_dev *clkdev); + + + + + + -static int omap3_clk_generic_activate(struct ti_clock_dev *clkdev); -static int omap3_clk_generic_deactivate(struct ti_clock_dev *clkdev); -static int omap3_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); -static int omap3_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq); -static int omap3_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); -static int omap3_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); -static void omap3_prcm_reset(void); -static int omap3_clk_cpsw_activate(struct ti_clock_dev *clkdev); -static int omap3_clk_musb0_activate(struct ti_clock_dev *clkdev); /** * omap_clk_devmap - Array of clock devices available on OMAP3xxx devices @@ -176,10 +222,9 @@ } +const struct ti_clock_dev omap_clk_devmap[] = { - -struct ti_clock_dev ti_clk_devmap[] = { - /* System clocks */ + /* System clock */ { .id = SYS_CLK, .clk_activate = NULL, .clk_deactivate = NULL, @@ -195,373 +240,320 @@ .clk_accessible = NULL, .clk_get_source_freq = omap3_clk_get_arm_fclk_freq, }, - /* CPSW Ethernet Switch core clocks */ - { .id = CPSW_CLK, - .clk_activate = omap3_clk_cpsw_activate, - .clk_deactivate = NULL, - .clk_set_source = NULL, - .clk_accessible = NULL, - .clk_get_source_freq = NULL, - }, - /* Mentor USB HS controller core clocks */ - { .id = MUSB0_CLK, - .clk_activate = omap3_clk_musb0_activate, - .clk_deactivate = NULL, - .clk_set_source = NULL, - .clk_accessible = NULL, - .clk_get_source_freq = NULL, - }, - /* DMTimer */ - AM335X_GENERIC_CLOCK_DEV(DMTIMER2_CLK), - AM335X_GENERIC_CLOCK_DEV(DMTIMER3_CLK), - AM335X_GENERIC_CLOCK_DEV(DMTIMER4_CLK), - AM335X_GENERIC_CLOCK_DEV(DMTIMER5_CLK), - AM335X_GENERIC_CLOCK_DEV(DMTIMER6_CLK), - AM335X_GENERIC_CLOCK_DEV(DMTIMER7_CLK), + /* UART device clocks */ + OMAP3_GENERIC_CLOCK_DEV(UART1_CLK), + OMAP3_GENERIC_CLOCK_DEV(UART2_CLK), + OMAP3_GENERIC_CLOCK_DEV(UART3_CLK), + OMAP3_GENERIC_CLOCK_DEV(UART4_CLK), + + /* Timer device source clocks */ + OMAP3_GPTIMER_CLOCK_DEV(GPTIMER1_CLK), + OMAP3_GPTIMER_CLOCK_DEV(GPTIMER2_CLK), + OMAP3_GPTIMER_CLOCK_DEV(GPTIMER3_CLK), + OMAP3_GPTIMER_CLOCK_DEV(GPTIMER4_CLK), + OMAP3_GPTIMER_CLOCK_DEV(GPTIMER5_CLK), + OMAP3_GPTIMER_CLOCK_DEV(GPTIMER6_CLK), + OMAP3_GPTIMER_CLOCK_DEV(GPTIMER7_CLK), + OMAP3_GPTIMER_CLOCK_DEV(GPTIMER8_CLK), + OMAP3_GPTIMER_CLOCK_DEV(GPTIMER9_CLK), + OMAP3_GPTIMER_CLOCK_DEV(GPTIMER10_CLK), + OMAP3_GPTIMER_CLOCK_DEV(GPTIMER11_CLK), +#if 0 + /* MMC device clocks (MMC1 and MMC2 can have different input clocks) */ + OMAP3_GENERIC_CLOCK_DEV(MMC1_CLK), + OMAP3_GENERIC_CLOCK_DEV(MMC2_CLK), + OMAP3_GENERIC_CLOCK_DEV(MMC3_CLK), + + /* USB HS (high speed TLL, EHCI and OHCI) */ + OMAP3_GENERIC_CLOCK_DEV(USBTLL_CLK), + OMAP3_HSUSBHOST_CLOCK_DEV(USBHSHOST_CLK), /* GPIO */ - AM335X_GENERIC_CLOCK_DEV(GPIO0_CLK), - AM335X_GENERIC_CLOCK_DEV(GPIO1_CLK), - AM335X_GENERIC_CLOCK_DEV(GPIO2_CLK), - AM335X_GENERIC_CLOCK_DEV(GPIO3_CLK), - + OMAP3_GENERIC_CLOCK_DEV(GPIO1_CLK), + OMAP3_GENERIC_CLOCK_DEV(GPIO2_CLK), + OMAP3_GENERIC_CLOCK_DEV(GPIO3_CLK), + OMAP3_GENERIC_CLOCK_DEV(GPIO4_CLK), + OMAP3_GENERIC_CLOCK_DEV(GPIO5_CLK), + OMAP3_GENERIC_CLOCK_DEV(GPIO6_CLK), + /* I2C */ - AM335X_GENERIC_CLOCK_DEV(I2C0_CLK), - AM335X_GENERIC_CLOCK_DEV(I2C1_CLK), - AM335X_GENERIC_CLOCK_DEV(I2C2_CLK), - - /* EDMA */ - AM335X_GENERIC_CLOCK_DEV(EDMA_TPCC_CLK), - AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC0_CLK), - AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC1_CLK), - AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC2_CLK), - - /* MMCHS */ - AM335X_MMCHS_CLOCK_DEV(MMC0_CLK), - AM335X_MMCHS_CLOCK_DEV(MMC1_CLK), - AM335X_MMCHS_CLOCK_DEV(MMC2_CLK), - + OMAP3_GENERIC_CLOCK_DEV(I2C1_CLK), + OMAP3_GENERIC_CLOCK_DEV(I2C2_CLK), + OMAP3_GENERIC_CLOCK_DEV(I2C3_CLK), + + /* sDMA */ + OMAP3_ALWAYSON_CLOCK_DEV(SDMA_CLK), +#endif { INVALID_CLK_IDENT, NULL, NULL, NULL, NULL } }; -struct omap3_clk_details { - clk_ident_t id; - uint32_t clkctrl_reg; - uint32_t clksel_reg; -}; -#define _CLK_DETAIL(i, c, s) \ - { .id = (i), \ - .clkctrl_reg = (c), \ - .clksel_reg = (s), \ - } -static struct omap3_clk_details g_omap3_clk_details[] = { - /* DMTimer modules */ - _CLK_DETAIL(DMTIMER2_CLK, CM_PER_TIMER2_CLKCTRL, CLKSEL_TIMER2_CLK), - _CLK_DETAIL(DMTIMER3_CLK, CM_PER_TIMER3_CLKCTRL, CLKSEL_TIMER3_CLK), - _CLK_DETAIL(DMTIMER4_CLK, CM_PER_TIMER4_CLKCTRL, CLKSEL_TIMER4_CLK), - _CLK_DETAIL(DMTIMER5_CLK, CM_PER_TIMER5_CLKCTRL, CLKSEL_TIMER5_CLK), - _CLK_DETAIL(DMTIMER6_CLK, CM_PER_TIMER6_CLKCTRL, CLKSEL_TIMER6_CLK), - _CLK_DETAIL(DMTIMER7_CLK, CM_PER_TIMER7_CLKCTRL, CLKSEL_TIMER7_CLK), - /* GPIO modules */ - _CLK_DETAIL(GPIO0_CLK, CM_WKUP_GPIO0_CLKCTRL, 0), - _CLK_DETAIL(GPIO1_CLK, CM_PER_GPIO1_CLKCTRL, 0), - _CLK_DETAIL(GPIO2_CLK, CM_PER_GPIO2_CLKCTRL, 0), - _CLK_DETAIL(GPIO3_CLK, CM_PER_GPIO3_CLKCTRL, 0), - /* I2C modules */ - _CLK_DETAIL(I2C0_CLK, CM_WKUP_I2C0_CLKCTRL, 0), - _CLK_DETAIL(I2C1_CLK, CM_PER_I2C1_CLKCTRL, 0), - _CLK_DETAIL(I2C2_CLK, CM_PER_I2C2_CLKCTRL, 0), - - /* EDMA modules */ - _CLK_DETAIL(EDMA_TPCC_CLK, CM_PER_TPCC_CLKCTRL, 0), - _CLK_DETAIL(EDMA_TPTC0_CLK, CM_PER_TPTC0_CLKCTRL, 0), - _CLK_DETAIL(EDMA_TPTC1_CLK, CM_PER_TPTC1_CLKCTRL, 0), - _CLK_DETAIL(EDMA_TPTC2_CLK, CM_PER_TPTC2_CLKCTRL, 0), - - /* MMCHS modules*/ - _CLK_DETAIL(MMC0_CLK, CM_PER_MMC0_CLKCTRL, 0), - _CLK_DETAIL(MMC1_CLK, CM_PER_MMC1_CLKCTRL, 0), - _CLK_DETAIL(MMC2_CLK, CM_PER_MMC1_CLKCTRL, 0), +/** + * g_omap3_clk_details - Stores details for all the different clocks supported + * + * Whenever an operation on a clock is being performed (activated, deactivated, + * etc) this array is looked up to find the correct register and bit(s) we + * should be modifying. + * + */ - { INVALID_CLK_IDENT, 0}, +struct omap3_clk_details { + clk_ident_t id; + int32_t src_freq; + + /* The register offset from the CM module register region of the registers*/ + uint32_t fclken_offset; + uint32_t iclken_offset; + uint32_t idlest_offset; + + /* The bit offset for the clock */ + uint32_t bit_offset; }; -/* Read/Write macros */ -#define prcm_read_4(reg) \ - bus_space_read_4(omap3_prcm_sc->bst, omap3_prcm_sc->bsh, reg) -#define prcm_write_4(reg, val) \ - bus_space_write_4(omap3_prcm_sc->bst, omap3_prcm_sc->bsh, reg, val) - -void omap3_prcm_setup_dmtimer(int); - -static int -omap3_prcm_probe(device_t dev) -{ - if (ofw_bus_is_compatible(dev, "omap3,prcm")) { - device_set_desc(dev, "AM335x Power and Clock Management"); - return(BUS_PROBE_DEFAULT); +#define OMAP3_GENERIC_CLOCK_DETAILS(d, freq, base, fclk, iclk, idlest, bit) \ + { .id = (d), \ + .src_freq = (freq), \ + .fclken_offset = ((base) + (fclk)), \ + .iclken_offset = ((base) + (iclk)), \ + .idlest_offset = ((base) + (idlest)), \ + .bit_offset = (bit), \ } - return (ENXIO); -} - -static int -omap3_prcm_attach(device_t dev) -{ - struct omap3_prcm_softc *sc = device_get_softc(dev); - unsigned int sysclk, fclk; - - if (omap3_prcm_sc) - return (ENXIO); +static const struct omap3_clk_details g_omap3_clk_details[] = { - if (bus_alloc_resources(dev, omap3_prcm_spec, sc->res)) { - device_printf(dev, "could not allocate resources\n"); - return (ENXIO); - } + /* UART */ + OMAP3_GENERIC_CLOCK_DETAILS(UART1_CLK, FREQ_48MHZ, CORE_CM_OFFSET, + 0x00, 0x10, 0x20, 13), + OMAP3_GENERIC_CLOCK_DETAILS(UART2_CLK, FREQ_48MHZ, CORE_CM_OFFSET, + 0x00, 0x10, 0x20, 14), + OMAP3_GENERIC_CLOCK_DETAILS(UART3_CLK, FREQ_48MHZ, PER_CM_OFFSET, + 0x00, 0x10, 0x20, 11), + + /* General purpose timers */ + OMAP3_GENERIC_CLOCK_DETAILS(GPTIMER1_CLK, -1, WKUP_CM_OFFSET, + 0x00, 0x10, 0x20, 3), + OMAP3_GENERIC_CLOCK_DETAILS(GPTIMER2_CLK, -1, PER_CM_OFFSET, + 0x00, 0x10, 0x20, 3), + OMAP3_GENERIC_CLOCK_DETAILS(GPTIMER3_CLK, -1, PER_CM_OFFSET, + 0x00, 0x10, 0x20, 4), + OMAP3_GENERIC_CLOCK_DETAILS(GPTIMER4_CLK, -1, PER_CM_OFFSET, + 0x00, 0x10, 0x20, 5), + OMAP3_GENERIC_CLOCK_DETAILS(GPTIMER5_CLK, -1, PER_CM_OFFSET, + 0x00, 0x10, 0x20, 6), + OMAP3_GENERIC_CLOCK_DETAILS(GPTIMER6_CLK, -1, PER_CM_OFFSET, + 0x00, 0x10, 0x20, 7), + OMAP3_GENERIC_CLOCK_DETAILS(GPTIMER7_CLK, -1, PER_CM_OFFSET, + 0x00, 0x10, 0x20, 8), + OMAP3_GENERIC_CLOCK_DETAILS(GPTIMER8_CLK, -1, PER_CM_OFFSET, + 0x00, 0x10, 0x20, 9), + OMAP3_GENERIC_CLOCK_DETAILS(GPTIMER9_CLK, -1, PER_CM_OFFSET, + 0x00, 0x10, 0x20, 10), + OMAP3_GENERIC_CLOCK_DETAILS(GPTIMER10_CLK, -1, CORE_CM_OFFSET, + 0x00, 0x10, 0x20, 11), + OMAP3_GENERIC_CLOCK_DETAILS(GPTIMER11_CLK, -1, CORE_CM_OFFSET, + 0x00, 0x10, 0x20, 12), +#if 0 + /* HSMMC (MMC1 and MMC2 can have different input clocks) */ + OMAP3_GENERIC_CLOCK_DETAILS(MMC1_CLK, FREQ_96MHZ, CORE_CM_OFFSET, + 0x00, 0x10, 0x20, 24), + OMAP3_GENERIC_CLOCK_DETAILS(MMC2_CLK, FREQ_96MHZ, CORE_CM_OFFSET, + 0x00, 0x10, 0x20, 25), + OMAP3_GENERIC_CLOCK_DETAILS(MMC3_CLK, FREQ_96MHZ, CORE_CM_OFFSET, + 0x00, 0x10, 0x20, 30), + + /* USB HS (high speed TLL, EHCI and OHCI) */ + OMAP3_GENERIC_CLOCK_DETAILS(USBTLL_CLK, -1, CORE_CM_OFFSET, + 0x08, 0x18, 0x28, 2), + OMAP3_GENERIC_CLOCK_DETAILS(USBHSHOST_CLK, -1, USBHOST_CM_OFFSET, + 0x00, 0x10, 0x20, 1), - sc->bst = rman_get_bustag(sc->res[0]); - sc->bsh = rman_get_bushandle(sc->res[0]); + /* GPIO modules */ + OMAP3_GENERIC_CLOCK_DETAILS(GPIO1_CLK, -1, WKUP_CM_OFFSET, + 0x00, 0x10, 0x20, 3), + OMAP3_GENERIC_CLOCK_DETAILS(GPIO2_CLK, -1, PER_CM_OFFSET, + 0x00, 0x10, 0x20, 13), + OMAP3_GENERIC_CLOCK_DETAILS(GPIO3_CLK, -1, PER_CM_OFFSET, + 0x00, 0x10, 0x20, 14), + OMAP3_GENERIC_CLOCK_DETAILS(GPIO4_CLK, -1, PER_CM_OFFSET, + 0x00, 0x10, 0x20, 15), + OMAP3_GENERIC_CLOCK_DETAILS(GPIO5_CLK, -1, PER_CM_OFFSET, + 0x00, 0x10, 0x20, 16), + OMAP3_GENERIC_CLOCK_DETAILS(GPIO6_CLK, -1, PER_CM_OFFSET, + 0x00, 0x10, 0x20, 17), + + /* I2C modules */ + OMAP3_GENERIC_CLOCK_DETAILS(I2C1_CLK, -1, CORE_CM_OFFSET, + 0x00, 0x10, 0x20, 15), + OMAP3_GENERIC_CLOCK_DETAILS(I2C2_CLK, -1, CORE_CM_OFFSET, + 0x00, 0x10, 0x20, 16), + OMAP3_GENERIC_CLOCK_DETAILS(I2C3_CLK, -1, CORE_CM_OFFSET, + 0x00, 0x10, 0x20, 17), +#endif - omap3_prcm_sc = sc; - ti_cpu_reset = omap3_prcm_reset; + { INVALID_CLK_IDENT, 0, 0, 0, 0 }, +}; - omap3_clk_get_sysclk_freq(NULL, &sysclk); - omap3_clk_get_arm_fclk_freq(NULL, &fclk); - device_printf(dev, "Clocks: System %u.%01u MHz, CPU %u MHz\n", - sysclk/1000000, (sysclk % 1000000)/100000, fclk/1000000); +static struct omap3_prcm_softc *omap3_prcm_sc = NULL; - return (0); -} -static device_method_t omap3_prcm_methods[] = { - DEVMETHOD(device_probe, omap3_prcm_probe), - DEVMETHOD(device_attach, omap3_prcm_attach), - { 0, 0 } -}; +/** + * MAX_MODULE_ENABLE_WAIT - the number of loops to wait for the module to come + * alive. + * + */ +#define MAX_MODULE_ENABLE_WAIT 1000 -static driver_t omap3_prcm_driver = { - "omap3_prcm", - omap3_prcm_methods, - sizeof(struct omap3_prcm_softc), -}; + +/** + * ARRAY_SIZE - Macro to return the number of elements in a static const array. + * + */ +#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) -static devclass_t omap3_prcm_devclass; -DRIVER_MODULE(omap3_prcm, simplebus, omap3_prcm_driver, - omap3_prcm_devclass, 0, 0); -MODULE_DEPEND(omap3_prcm, ti_scm, 1, 1, 1); -static struct omap3_clk_details* -omap3_clk_details(clk_ident_t id) +static int +omap3_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq) { - struct omap3_clk_details *walker; - - for (walker = g_omap3_clk_details; walker->id != INVALID_CLK_IDENT; walker++) { - if (id == walker->id) - return (walker); - } + + return (0); +} - return NULL; +static int +omap3_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq) +{ + + return (0); } static int omap3_clk_generic_activate(struct ti_clock_dev *clkdev) { - struct omap3_prcm_softc *sc = omap3_prcm_sc; - struct omap3_clk_details* clk_details; - - if (sc == NULL) - return ENXIO; - - clk_details = omap3_clk_details(clkdev->id); - - if (clk_details == NULL) - return (ENXIO); - - /* set *_CLKCTRL register MODULEMODE[1:0] to enable(2) */ - prcm_write_4(clk_details->clkctrl_reg, 2); - while ((prcm_read_4(clk_details->clkctrl_reg) & 0x3) != 2) - DELAY(10); - + return (0); } static int omap3_clk_generic_deactivate(struct ti_clock_dev *clkdev) { - struct omap3_prcm_softc *sc = omap3_prcm_sc; - struct omap3_clk_details* clk_details; - - if (sc == NULL) - return ENXIO; - - clk_details = omap3_clk_details(clkdev->id); - - if (clk_details == NULL) - return (ENXIO); - - /* set *_CLKCTRL register MODULEMODE[1:0] to disable(0) */ - prcm_write_4(clk_details->clkctrl_reg, 0); - while ((prcm_read_4(clk_details->clkctrl_reg) & 0x3) != 0) - DELAY(10); - + return (0); } static int omap3_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc) { - struct omap3_prcm_softc *sc = omap3_prcm_sc; - struct omap3_clk_details* clk_details; - uint32_t reg; - - if (sc == NULL) - return ENXIO; - - clk_details = omap3_clk_details(clkdev->id); - - if (clk_details == NULL) - return (ENXIO); - - switch (clksrc) { - case EXT_CLK: - reg = 0; /* SEL2: TCLKIN clock */ - break; - case SYSCLK_CLK: - reg = 1; /* SEL1: CLK_M_OSC clock */ - break; - case F32KHZ_CLK: - reg = 2; /* SEL3: CLK_32KHZ clock */ - break; - default: - return (ENXIO); - } - - prcm_write_4(clk_details->clksel_reg, reg); - while ((prcm_read_4(clk_details->clksel_reg) & 0x3) != reg) - DELAY(10); - + return (0); } static int -omap3_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq) +omap3_clk_generic_accessible(struct ti_clock_dev *clkdev) { - *freq = 96000000; + return (0); } -static int -omap3_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq) + +/** + * omap3_clk_init - add a child item to the root omap3 device + * @dev: the parent device + * @prio: defines roughly the order with which to add the child to the parent + * + * Initialises the clock structure and add an instance of the omap_prcm to + * the parent device with the correct memory regions assigned. + * + * + */ +void +omap3_clk_init(device_t dev, int prio) { - uint32_t ctrl_status; + device_t kid; + struct omap_ivar *ivar; - /* Read the input clock freq from the control module */ - /* control_status reg (0x40) */ - if (ti_scm_reg_read_4(0x40, &ctrl_status)) - return ENXIO; - - switch ((ctrl_status>>22) & 0x3) { - case 0x0: - /* 19.2Mhz */ - *freq = 19200000; - break; - case 0x1: - /* 24Mhz */ - *freq = 24000000; - break; - case 0x2: - /* 25Mhz */ - *freq = 25000000; - break; - case 0x3: - /* 26Mhz */ - *freq = 26000000; - break; + /* Start by adding the actual child to the parent (us) */ + kid = device_add_child_ordered(dev, prio, "omap_prcm", 0); + if (kid == NULL) { + printf("Can't add child omap_prcm0 ordered\n"); + return; } - - return (0); + + /* Allocate some memory for the omap_ivar structure */ + ivar = malloc(sizeof(*ivar), M_DEVBUF, M_NOWAIT | M_ZERO); + if (ivar == NULL) { + device_delete_child(dev, kid); + printf("Can't add alloc ivar\n"); + return; + } + + /* Assign the ivars to the child item and populate with the device resources */ + device_set_ivars(kid, ivar); + + /* Assign the IRQ(s) in the resource list */ + resource_list_init(&ivar->resources); + + /* Assign the memory region to the resource list */ + bus_set_resource(kid, SYS_RES_MEMORY, CM_INSTANCE_MEM_REGION, + OMAP35XX_CM_HWBASE, 0x2000); + bus_set_resource(kid, SYS_RES_MEMORY, PRM_INSTANCE_MEM_REGION, + OMAP35XX_PRM_HWBASE, 0x2000); } static int -omap3_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq) -{ - uint32_t reg; - uint32_t sysclk; -#define DPLL_BYP_CLKSEL(reg) ((reg>>23) & 1) -#define DPLL_DIV(reg) ((reg & 0x7f)+1) -#define DPLL_MULT(reg) ((reg>>8) & 0x7FF) - - reg = prcm_read_4(CM_WKUP_CM_CLKSEL_DPLL_MPU); - - /*Check if we are running in bypass */ - if (DPLL_BYP_CLKSEL(reg)) - return ENXIO; - - omap3_clk_get_sysclk_freq(NULL, &sysclk); - *freq = DPLL_MULT(reg) * (sysclk / DPLL_DIV(reg)); - return(0); -} - -static void -omap3_prcm_reset(void) +omap3_prcm_probe(device_t dev) { - prcm_write_4(PRM_RSTCTRL, (1<<1)); + if (ofw_bus_is_compatible(dev, "am37x,prcm")) { + device_set_desc(dev, "OMAP3 Power and Clock Management"); + return(BUS_PROBE_DEFAULT); + } + return (ENXIO); } static int -omap3_clk_cpsw_activate(struct ti_clock_dev *clkdev) +omap3_prcm_attach(device_t dev) { - struct omap3_prcm_softc *sc = omap3_prcm_sc; - - if (sc == NULL) - return ENXIO; + struct omap3_prcm_softc *sc = device_get_softc(dev); - /* set MODULENAME to ENABLE */ - prcm_write_4(CM_PER_CPGMAC0_CLKCTRL, 2); + if( omap3_prcm_sc ) + { + return (ENXIO); + } + if( bus_alloc_resources(dev, omap3_prcm_spec, sc->res ) ) + { + device_printf(dev, "could not allocate resources\n" ); + return (ENXIO); + } - /* wait for IDLEST to become Func(0) */ - while(prcm_read_4(CM_PER_CPGMAC0_CLKCTRL) & (3<<16)); + sc->cm_bst = rman_get_bustag(sc->res[0]); + sc->cm_bsh = rman_get_bushandle(sc->res[0]); + sc->prm_bst = rman_get_bustag(sc->res[1]); + sc->prm_bsh = rman_get_bushandle(sc->res[1]); + omap3_prcm_sc = sc; - /*set CLKTRCTRL to SW_WKUP(2) */ - prcm_write_4(CM_PER_CPSW_CLKSTCTRL, 2); - /* wait for 125 MHz OCP clock to become active */ - while((prcm_read_4(CM_PER_CPSW_CLKSTCTRL) & (1<<4)) == 0); - return(0); + return (0); } -static int -omap3_clk_musb0_activate(struct ti_clock_dev *clkdev) -{ - struct omap3_prcm_softc *sc = omap3_prcm_sc; - - if (sc == NULL) - return ENXIO; - - /* set ST_DPLL_CLKDCOLDO(9) to CLK_GATED(1) */ - /* set DPLL_CLKDCOLDO_GATE_CTRL(8) to CLK_ENABLE(1)*/ - prcm_write_4(CM_WKUP_CM_CLKDCOLDO_DPLL_PER, 0x300); - - /*set MODULEMODE to ENABLE(2) */ - prcm_write_4(CM_PER_USB0_CLKCTRL, 2); - - /* wait for MODULEMODE to become ENABLE(2) */ - while ((prcm_read_4(CM_PER_USB0_CLKCTRL) & 0x3) != 2) - DELAY(10); +static device_method_t omap3_prcm_methods[] = { + DEVMETHOD(device_probe, omap3_prcm_probe), + DEVMETHOD(device_attach, omap3_prcm_attach), + { 0, 0 } +}; - /* wait for IDLEST to become Func(0) */ - while(prcm_read_4(CM_PER_USB0_CLKCTRL) & (3<<16)) - DELAY(10); +static driver_t omap3_prcm_driver = { + "omap3_prcm", + omap3_prcm_methods, + sizeof(struct omap3_prcm_softc), +}; - return(0); -} +static devclass_t omap3_prcm_devclass; +DRIVER_MODULE(omap3_prcm, simplebus, omap3_prcm_driver, omap3_prcm_devclass, 0, 0); +MODULE_DEPEND(omap3_prcm, ti_scm, 1, 1, 1); Modified: soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts ============================================================================== --- soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts Mon Jun 18 11:49:23 2012 (r237888) +++ soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts Mon Jun 18 12:33:37 2012 (r237889) @@ -69,11 +69,12 @@ "I2C0_SCL", "I2C0_SCL","input_pullup_inact_slow"; }; - prcm@44E00000 { - compatible = "am37x,prcm"; + prcm@48004000 { + compatible = "am37x,omap3_prcm"; #address-cells = <1>; #size-cells = <1>; - reg = < 0x44E00000 0x1300 >; + reg = < 0x48004000 0x2000 + 0x48306000 0x2000>; }; GPIO: gpio {