From owner-cvs-all Sat Jul 27 15: 9: 9 2002 Delivered-To: cvs-all@freebsd.org Received: from mx1.FreeBSD.org (mx1.FreeBSD.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 796C337B405 for ; Sat, 27 Jul 2002 15:09:01 -0700 (PDT) Received: from mail.speakeasy.net (mail12.speakeasy.net [216.254.0.212]) by mx1.FreeBSD.org (Postfix) with ESMTP id 0A5A043E31 for ; Sat, 27 Jul 2002 15:09:01 -0700 (PDT) (envelope-from jhb@FreeBSD.org) Received: (qmail 18817 invoked from network); 27 Jul 2002 22:08:59 -0000 Received: from unknown (HELO server.baldwin.cx) ([216.27.160.63]) (envelope-sender ) by mail12.speakeasy.net (qmail-ldap-1.03) with DES-CBC3-SHA encrypted SMTP for ; 27 Jul 2002 22:08:59 -0000 Received: from laptop.baldwin.cx (laptop.baldwin.cx [192.168.0.4]) by server.baldwin.cx (8.12.5/8.12.5) with ESMTP id g6RM8wuR045946; Sat, 27 Jul 2002 18:08:58 -0400 (EDT) (envelope-from jhb@FreeBSD.org) Message-ID: X-Mailer: XFMail 1.5.2 on FreeBSD X-Priority: 3 (Normal) Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 8bit MIME-Version: 1.0 In-Reply-To: <200207272157.g6RLvcSU040080@freefall.freebsd.org> Date: Sat, 27 Jul 2002 18:09:06 -0400 (EDT) From: John Baldwin To: Jake Burkholder Subject: RE: cvs commit: src/sys/sparc64/include pmap.h tlb.h src/sys/spa Cc: cvs-all@FreeBSD.org, cvs-committers@FreeBSD.org Sender: owner-cvs-all@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.ORG On 27-Jul-2002 Jake Burkholder wrote: > jake 2002/07/27 14:57:38 PDT > > Modified files: > sys/sparc64/include pmap.h tlb.h > sys/sparc64/sparc64 exception.s genassym.c pmap.c > Log: > Implement a direct mapped address region, like alpha and ia64. This > basically maps all of physical memory 1:1 to a range of virtual addresses > outside of normal kva. The advantage of doing this instead of accessing > phsyical addresses directly is that memory accesses will go through the > data cache, and will participate in the normal cache coherency algorithm > for invalidating lines in our own and in other cpus' data caches. So > we don't have to flush the cache manually or send IPIs to do so on other > cpus. Also, since the mappings never change, we don't have to flush them > from the tlb manually. > This makes pmap_copy_page and pmap_zero_page MP safe, allowing the idle > zero proc to run outside of giant. > > Inspired by: ia64 Woot! -- John Baldwin <>< http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve!" - http://www.FreeBSD.org/ To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe cvs-all" in the body of the message