Date: Thu, 13 Sep 2012 19:05:24 +0000 (UTC) From: John Baldwin <jhb@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r240473 - head/sys/dev/pci Message-ID: <201209131905.q8DJ5OMY056609@svn.freebsd.org>
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Author: jhb Date: Thu Sep 13 19:05:24 2012 New Revision: 240473 URL: http://svn.freebsd.org/changeset/base/240473 Log: - Add some registers defined in PCI 3.0 including new AER bits. - Add constants for the rest of the fields in the PCI-express device capability and control registers. - Tweak some of the recently added PCI-e capability constants (always use hex for offsets in config space, and include a shortened version of the relevant register in the name of field constants). MFC after: 1 week Modified: head/sys/dev/pci/pcireg.h Modified: head/sys/dev/pci/pcireg.h ============================================================================== --- head/sys/dev/pci/pcireg.h Thu Sep 13 18:47:24 2012 (r240472) +++ head/sys/dev/pci/pcireg.h Thu Sep 13 19:05:24 2012 (r240473) @@ -64,6 +64,7 @@ #define PCIM_CMD_BACKTOBACK 0x0200 #define PCIM_CMD_INTxDIS 0x0400 #define PCIR_STATUS 0x06 +#define PCIM_STATUS_INTxSTATE 0x0008 #define PCIM_STATUS_CAPPRESENT 0x0010 #define PCIM_STATUS_66CAPABLE 0x0020 #define PCIM_STATUS_BACKTOBACK 0x0080 @@ -134,11 +135,22 @@ #define PCIZ_VC 0x0002 /* Virtual Channel */ #define PCIZ_SERNUM 0x0003 /* Device Serial Number */ #define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */ +#define PCIZ_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */ +#define PCIZ_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */ +#define PCIZ_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */ +#define PCIZ_MFVC 0x0008 /* Multi-Function Virtual Channel */ +#define PCIZ_RCRB 0x000a /* RCRB Header */ #define PCIZ_VENDOR 0x000b /* Vendor Unique */ #define PCIZ_ACS 0x000d /* Access Control Services */ #define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */ #define PCIZ_ATS 0x000f /* Address Translation Services */ #define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */ +#define PCIZ_MULTICAST 0x0012 /* Multicast */ +#define PCIZ_RESIZE_BAR 0x0015 /* Resizable BAR */ +#define PCIZ_DPA 0x0016 /* Dynamic Power Allocation */ +#define PCIZ_TPH_REQ 0x0017 /* TPH Requester */ +#define PCIZ_LTR 0x0018 /* Latency Tolerance Reporting */ +#define PCIZ_SEC_PCIE 0x0019 /* Secondary PCI Express */ /* config registers for header type 0 devices */ @@ -632,15 +644,29 @@ #define PCIM_EXP_FLAGS_SLOT 0x0100 #define PCIM_EXP_FLAGS_IRQ 0x3e00 #define PCIR_EXPRESS_DEVICE_CAP 0x4 -#define PCIM_EXP_CAP_MAX_PAYLOAD 0x0007 +#define PCIM_EXP_CAP_MAX_PAYLOAD 0x00000007 +#define PCIM_EXP_CAP_PHANTHOM_FUNCS 0x00000018 +#define PCIM_EXP_CAP_EXT_TAG_FIELD 0x00000020 +#define PCIM_EXP_CAP_L0S_LATENCY 0x000001c0 +#define PCIM_EXP_CAP_L1_LATENCY 0x00000e00 +#define PCIM_EXP_CAP_ROLE_ERR_RPT 0x00008000 +#define PCIM_EXP_CAP_SLOT_PWR_LIM_VAL 0x03fc0000 +#define PCIM_EXP_CAP_SLOT_PWR_LIM_SCALE 0x0c000000 +#define PCIM_EXP_CAP_FLR 0x10000000 #define PCIR_EXPRESS_DEVICE_CTL 0x8 +#define PCIM_EXP_CTL_COR_ENABLE 0x0001 #define PCIM_EXP_CTL_NFER_ENABLE 0x0002 #define PCIM_EXP_CTL_FER_ENABLE 0x0004 #define PCIM_EXP_CTL_URR_ENABLE 0x0008 #define PCIM_EXP_CTL_RELAXED_ORD_ENABLE 0x0010 #define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0 +#define PCIM_EXP_CTL_EXT_TAG_FIELD 0x0100 +#define PCIM_EXP_CTL_PHANTHOM_FUNCS 0x0200 +#define PCIM_EXP_CTL_AUX_POWER_PM 0x0400 #define PCIM_EXP_CTL_NOSNOOP_ENABLE 0x0800 #define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000 +#define PCIM_EXP_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */ +#define PCIM_EXP_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */ #define PCIR_EXPRESS_DEVICE_STA 0xa #define PCIM_EXP_STA_CORRECTABLE_ERROR 0x0001 #define PCIM_EXP_STA_NON_FATAL_ERROR 0x0002 @@ -654,6 +680,11 @@ #define PCIM_LINK_CAP_ASPM 0x00000c00 #define PCIM_LINK_CAP_L0S_EXIT 0x00007000 #define PCIM_LINK_CAP_L1_EXIT 0x00038000 +#define PCIM_LINK_CAP_CLOCK_PM 0x00040000 +#define PCIM_LINK_CAP_SURPRISE_DOWN 0x00080000 +#define PCIM_LINK_CAP_DL_ACTIVE 0x00100000 +#define PCIM_LINK_CAP_LINK_BW_NOTIFY 0x00200000 +#define PCIM_LINK_CAP_ASPM_COMPLIANCE 0x00400000 #define PCIM_LINK_CAP_PORT 0xff000000 #define PCIR_EXPRESS_LINK_CTL 0x10 #define PCIR_EXPRESS_LINK_STA 0x12 @@ -662,6 +693,9 @@ #define PCIM_LINK_STA_TRAINING_ERROR 0x0400 #define PCIM_LINK_STA_TRAINING 0x0800 #define PCIM_LINK_STA_SLOT_CLOCK 0x1000 +#define PCIM_LINK_STA_DL_ACTIVE 0x2000 +#define PCIM_LINK_STA_LINK_BW_MGMT 0x4000 +#define PCIM_LINK_STA_LINK_AUTO_BW 0x8000 #define PCIR_EXPRESS_SLOT_CAP 0x14 #define PCIM_EXP_SLOT_CAP_APB 0x00000001 #define PCIM_EXP_SLOT_CAP_PCP 0x00000002 @@ -699,16 +733,29 @@ #define PCIM_EXP_SLOT_STA_DLLSC 0x0100 #define PCIR_EXPRESS_ROOT_CTL 0x1c #define PCIR_EXPRESS_ROOT_STA 0x20 -#define PCIR_EXPRESS_DEVICE_CTL2 40 -#define PCIM_EXPRESS_DEVICE_CTL2_ARI 0x20 -#define PCIM_EXPRESS_ID_ORDERED_REQ_EN 0x100 -#define PCIM_EXPRESS_ID_ORDERED_CMP_EN 0x200 -#define PCIM_EXPRESS_LTR_ENABLE 0x400 -#define PCIM_EXPRESS_OBFF_MSGA_ENABLE 0x2000 -#define PCIM_EXPRESS_OBFF_MSGB_ENABLE 0x4000 -#define PCIM_EXPRESS_OBFF_WAKE_ENABLE 0x6000 -#define PCIR_EXPRESS_LINK_CTL2 48 -#define PCIR_EXPRESS_SLOT_CTL2 56 +#define PCIR_EXPRESS_DEVICE_CAP2 0x24 +#define PCIR_EXPRESS_DEVICE_CTL2 0x28 +#define PCIM_EXP_CTL2_COMP_TIMEOUT_VAL 0x000f +#define PCIM_EXP_CTL2_COMP_TIMEOUT_DIS 0x0010 +#define PCIM_EXP_CTL2_ARI 0x0020 +#define PCIM_EXP_CTL2_ATOMIC_REQ_ENABLE 0x0040 +#define PCIM_EXP_CTL2_ATOMIC_EGR_BLOCK 0x0080 +#define PCIM_EXP_CTL2_ID_ORDERED_REQ_EN 0x0100 +#define PCIM_EXP_CTL2_ID_ORDERED_CMP_EN 0x0200 +#define PCIM_EXP_CTL2_LTR_ENABLE 0x0400 +#define PCIM_EXP_CTL2_OBFF 0x6000 +#define PCIM_EXP_OBFF_DISABLE 0x0000 +#define PCIM_EXP_OBFF_MSGA_ENABLE 0x2000 +#define PCIM_EXP_OBFF_MSGB_ENABLE 0x4000 +#define PCIM_EXP_OBFF_WAKE_ENABLE 0x6000 +#define PCIM_EXP_CTL2_END2END_TLP 0x8000 +#define PCIR_EXPRESS_DEVICE_STA2 0x2a +#define PCIR_EXPRESS_LINK_CAP2 0x2c +#define PCIR_EXPRESS_LINK_CTL2 0x30 +#define PCIR_EXPRESS_LINK_STA2 0x32 +#define PCIR_EXPRESS_SLAT_CAP2 0x34 +#define PCIR_EXPRESS_SLOT_CTL2 0x38 +#define PCIR_EXPRESS_SLOT_STA2 0x3a /* MSI-X definitions */ #define PCIR_MSIX_CTRL 0x2 @@ -750,6 +797,10 @@ #define PCIM_AER_UC_ECRC_ERROR 0x00080000 #define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000 #define PCIM_AER_UC_ACS_VIOLATION 0x00200000 +#define PCIM_AER_UC_INTERNAL_ERROR 0x00400000 +#define PCIM_AER_UC_MC_BLOCKED_TLP 0x00800000 +#define PCIM_AER_UC_ATOMIC_EGRESS_BLK 0x01000000 +#define PCIM_AER_UC_TLP_PREFIX_BLOCKED 0x02000000 #define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */ #define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */ #define PCIR_AER_COR_STATUS 0x10 @@ -759,6 +810,8 @@ #define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100 #define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000 #define PCIM_AER_COR_ADVISORY_NF_ERROR 0x00002000 +#define PCIM_AER_COR_INTERNAL_ERROR 0x00004000 +#define PCIM_AER_COR_HEADER_LOG_OVFLOW 0x00008000 #define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */ #define PCIR_AER_CAP_CONTROL 0x18 #define PCIM_AER_FIRST_ERROR_PTR 0x0000001f @@ -766,6 +819,9 @@ #define PCIM_AER_ECRC_GEN_ENABLE 0x00000040 #define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080 #define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100 +#define PCIM_AER_MULT_HDR_CAPABLE 0x00000200 +#define PCIM_AER_MULT_HDR_ENABLE 0x00000400 +#define PCIM_AER_TLP_PREFIX_LOG_PRESENT 0x00000800 #define PCIR_AER_HEADER_LOG 0x1c #define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */ #define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001 @@ -782,6 +838,7 @@ #define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000 #define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */ #define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */ +#define PCIR_AER_TLP_PREFIX_LOG 0x38 /* Only for TLP prefix functions */ /* Virtual Channel definitions */ #define PCIR_VC_CAP1 0x04
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