From owner-freebsd-threads@FreeBSD.ORG Tue Mar 30 00:25:15 2004 Return-Path: Delivered-To: freebsd-threads@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 6775516A4CE for ; Tue, 30 Mar 2004 00:25:15 -0800 (PST) Received: from herring.rabson.org (mailgate.nlsystems.com [80.177.232.242]) by mx1.FreeBSD.org (Postfix) with ESMTP id 9B05643D2F for ; Tue, 30 Mar 2004 00:25:14 -0800 (PST) (envelope-from dfr@nlsystems.com) Received: from herring.rabson.org (herring.rabson.org [10.0.0.2]) by herring.rabson.org (8.12.11/8.12.11) with ESMTP id i2U8P2Ti015770; Tue, 30 Mar 2004 09:25:03 +0100 (BST) (envelope-from dfr@nlsystems.com) From: Doug Rabson To: Peter Wemm Date: Tue, 30 Mar 2004 09:25:02 +0100 User-Agent: KMail/1.6.1 References: <200403291518.33559.peter@wemm.org> In-Reply-To: <200403291518.33559.peter@wemm.org> MIME-Version: 1.0 Content-Disposition: inline Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <200403300925.02485.dfr@nlsystems.com> X-Spam-Status: No, hits=0.0 required=5.0 tests=none autolearn=no version=2.63 X-Spam-Checker-Version: SpamAssassin 2.63 (2004-01-11) on herring.rabson.org X-Virus-Scanned: ClamAV version 'clamd / ClamAV version 0.65', clamav-milter version '0.60p' cc: freebsd-threads@freebsd.org Subject: Re: Thread Local Storage X-BeenThere: freebsd-threads@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Threading on FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 30 Mar 2004 08:25:15 -0000 On Tuesday 30 March 2004 00:18, Peter Wemm wrote: > On Monday 29 March 2004 02:36 pm, Daniel Eischen wrote: > [..] > > > > > > You don't need a syscall at thread switch if you do something > > > > > like: > > > > > > > > > > _thread_switch(...) > > > > > { > > > > > if (tcb doesn't have LDT entry) { > > > > > if (!free LDT entries) > > > > > steal LDT entry from non-running thread; > > > > > allocate LDT entry and point it at TLS goop for tcb. > > > > > } > > > > > load_gs(tcb's LDT sel); > > > > > > > > That's a system call on amd64. > > > > > > I'm not quite up to speed on amd64. So in 64-bit mode it doesn't > > > really have an LDT at all, is that right? > > > > I'm not sure, but you have to make a system call to set it > > or it's equivalent (amd64_set_fsbase()). > > Correct. There are two ways to do these things on this cpu. One is > to use descriptor tables. The catch is that using descriptor tables > forces a 4GB limit. It won't wrap around. The other way is to write > to the MSRs for fsbase/gsbase. But the downside of that is that is a > priviliged operation and needs to be done in supervisor mode. What do you put in %fs and %gs for the non-table mode? The TLS ABI for amd64 is a 64bit equivalent to the GNU i386 ABI (with %fs instead of %gs). It also allows stuff like 'movq %fs:x@tpoff, %rax' where x@tpoff resolves to the negative offset from the end of the TLS block to the location of x. I can't see any way of avoiding setting fsbase on thread switch here. > > I don't *have* an LDT on the amd64 kernel. I'm dreading having to > emulate the i386 sysarch LDT stuff already. Segment registers. Not the worlds greatest idea...