From owner-freebsd-mips@FreeBSD.ORG Mon Nov 5 15:54:42 2012 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 40D2C2AC for ; Mon, 5 Nov 2012 15:54:42 +0000 (UTC) (envelope-from freebsd@pdx.rh.CN85.ChatUSA.com) Received: from pdx.rh.CN85.ChatUSA.com (pdx.rh.CN85.ip6.chatusa.com [IPv6:2607:fa80:104::6]) by mx1.freebsd.org (Postfix) with ESMTP id CFDE28FC0C for ; Mon, 5 Nov 2012 15:54:41 +0000 (UTC) Received: from pdx.rh.CN85.ChatUSA.com (localhost [127.0.0.1]) by pdx.rh.CN85.ChatUSA.com (8.13.3/8.13.3) with ESMTP id qA4J4NcT076639; Sun, 4 Nov 2012 11:04:23 -0800 (PST) (envelope-from freebsd@pdx.rh.CN85.ChatUSA.com) Received: (from freebsd@localhost) by pdx.rh.CN85.ChatUSA.com (8.13.3/8.13.3/Submit) id qA4ISomC076058; Sun, 4 Nov 2012 10:28:50 -0800 (PST) (envelope-from freebsd) From: "Rodney W. Grimes" Message-Id: <201211041828.qA4ISomC076058@pdx.rh.CN85.ChatUSA.com> Subject: Re: CACHE_LINE_SIZE macro. In-Reply-To: To: Juli Mallett Date: Sun, 4 Nov 2012 10:28:49 -0800 (PST) X-Mailer: ELM [version 2.4ME+ PL121h (25)] MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=US-ASCII Cc: "freebsd-mips@FreeBSD.org" X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 05 Nov 2012 15:54:42 -0000 The size of, geometry of, or even the existance of a cache should never appear in any ABI other than an ABI to query such data. There should also never be a compile time constant of a machine dependent value like this, it should be determined at boot/config time. If at all possible the use of this information should be well contained to a minimal set of code, as it SHALL change over time. Even if no MIPS CPU exists today with a 256 byte line, dont mean I won't decide to build one tomarrow. I might also decide to build one with a 2 byte line :-) What ABI is exposing anything about cache parameters or may be come dependent on such information? > Fellow FreeBSD/MIPSists, > > CACHE_LINE_SIZE is being used increasingly-much in ways which may have ABI > implications, etc. It is currentyl 2^6, whereas at least the Cavium Octeon > has cache lines that are actually 2^7 bytes in size. It would be nice to > expose the correct value to reduce false line sharing, etc., but making it > dependent on the CPU type raises ABI issues, as well as questions about how > to reliably get the right value to userland. It seems to me that > increasing it to 2^7 is the most viable approach, but I can imagine there > might be some concerns about that, so I wanted to run it past this list > first. Questions, comments, concerns? Are there MIPS CPUs with 2^8-byte > or larger cache lines that we support or will support or which are likely > coming over the horizon? > > Thanks, > Juli. > _______________________________________________ > freebsd-mips@freebsd.org mailing list > http://lists.freebsd.org/mailman/listinfo/freebsd-mips > To unsubscribe, send any mail to "freebsd-mips-unsubscribe@freebsd.org" > -- Rod Grimes freebsd@freebsd.org