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Fri, 06 Sep 2019 21:06:43 -0700 (PDT) MIME-Version: 1.0 References: <201909060119.x861JWrG006910@repo.freebsd.org> <4917d7507b6ea6c360dccda261f53052aa085f2b.camel@freebsd.org> <5EE266EE-E650-48D8-9B0E-E674AD026470@freebsd.org> <3cb6429acc7e520932d2c906d1cac47540156355.camel@freebsd.org> <8F03EA29-0F3F-4321-9241-78F7C924FDE1@freebsd.org> In-Reply-To: <8F03EA29-0F3F-4321-9241-78F7C924FDE1@freebsd.org> From: Warner Losh Date: Fri, 6 Sep 2019 22:06:32 -0600 Message-ID: Subject: Re: svn commit: r351918 - head/sys/kern To: Philip Paeps Cc: Ian Lepore , src-committers , svn-src-all , svn-src-head X-Rspamd-Queue-Id: 46QLTc2gRzz43vG X-Spamd-Bar: --- Authentication-Results: mx1.freebsd.org; dkim=pass header.d=bsdimp-com.20150623.gappssmtp.com header.s=20150623 header.b=BfYPx8yz; dmarc=none; spf=none (mx1.freebsd.org: domain of wlosh@bsdimp.com has no SPF policy when checking 2607:f8b0:4864:20::843) smtp.mailfrom=wlosh@bsdimp.com X-Spamd-Result: default: False [-3.49 / 15.00]; ARC_NA(0.00)[]; NEURAL_HAM_MEDIUM(-1.00)[-1.000,0]; R_DKIM_ALLOW(-0.20)[bsdimp-com.20150623.gappssmtp.com:s=20150623]; FROM_HAS_DN(0.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000,0]; MIME_GOOD(-0.10)[multipart/alternative,text/plain]; PREVIOUSLY_DELIVERED(0.00)[svn-src-all@freebsd.org]; DMARC_NA(0.00)[bsdimp.com]; RCPT_COUNT_FIVE(0.00)[5]; TO_MATCH_ENVRCPT_SOME(0.00)[]; TO_DN_ALL(0.00)[]; DKIM_TRACE(0.00)[bsdimp-com.20150623.gappssmtp.com:+]; NEURAL_HAM_SHORT(-0.98)[-0.983,0]; RCVD_IN_DNSWL_NONE(0.00)[3.4.8.0.0.0.0.0.0.0.0.0.0.0.0.0.0.2.0.0.4.6.8.4.0.b.8.f.7.0.6.2.list.dnswl.org : 127.0.5.0]; R_SPF_NA(0.00)[]; FORGED_SENDER(0.30)[imp@bsdimp.com,wlosh@bsdimp.com]; MIME_TRACE(0.00)[0:+,1:+,2:~]; IP_SCORE(-0.50)[ip: (2.55), ipnet: 2607:f8b0::/32(-2.75), asn: 15169(-2.27), country: US(-0.05)]; ASN(0.00)[asn:15169, ipnet:2607:f8b0::/32, country:US]; FROM_NEQ_ENVFROM(0.00)[imp@bsdimp.com,wlosh@bsdimp.com]; RCVD_TLS_ALL(0.00)[]; RCVD_COUNT_TWO(0.00)[2] Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 07 Sep 2019 04:06:45 -0000 On Fri, Sep 6, 2019 at 9:54 PM Philip Paeps wrote: > On 2019-09-06 22:18:36 (+0800), Ian Lepore wrote: > > On Fri, 2019-09-06 at 12:15 +0800, Philip Paeps wrote: > >> On 2019-09-06 11:15:12 (+0800), Ian Lepore wrote: > >>> On Fri, 2019-09-06 at 01:19 +0000, Philip Paeps wrote: > >>>> Log: > >>>> riscv: default to HZ=100 > >>> > >>> This seems like a bad idea. I've run a 90mhz armv4 chip with > >>> HZ=1000 and didn't notice any performance hit from doing so. Almost > >>> all arm kernel config files set HZ as an option, so that define > >>> doesn't do much for arm these days. It probably does still set HZ > >>> for various mips platforms. > >>> > >>> I would think 1000 is appropriate for anything modern running at > >>> 200mhz or more. > >>> > >>> Setting it to 100 has the bad side effect of making things like > >>> msleep(), tsleep(), and pause() (which show up in plenty of drivers) > >>> all have a minimum timeout of 10ms, which is a long long time on > >>> modern hardware. > >>> > >>> What benefit do you think you'll get from the lower number? > >> > >> On systems running at 10s of MHz (or slower, ick), with HZ=1000 you > >> spend an awful lot of time servicing the timer interrupt and not very > >> much time doing anything else. > >> > >> My rationale was that most RISC-V systems (including emulation and > >> FPGA prototypes) I've encountered are running slower than the tipping > >> point where HZ=1000 makes sense. With the default of HZ=100, faster > >> exceptions can still set HZ=1000 in their individual configs. > >> > >> When the RISC-V world evolves to having more actual silicon and fewer > >> slow prototypes, I definitely agree this default should be flipped > >> again for HZ=1000 by default and HZ=100 in the config files for the > >> exceptions. > > > > Wait a second... are you saying that the riscv implementation doesn't > > support event timers and uses an old-style periodic tick based on HZ? > > Depending on the hardware, there may not be an event timer (yet)... > > As I wrote: I would be more than happy to revert this change when more > silicon becomes available. Presently, there is exactly one silicon > RISC-V implementation commercially available (HiFive FU540) and even > that one is kind of difficult to source. Most people running RISC-V are > doing so in emulation or on FPGAs. > > Given how long these things take to boot to userland (where you really > notice how slow things are), HZ=100 feels like a more sensible default > than HZ=1000. > I think it show more that the defaults are bad for MIPS and ARM. All the MIPS files, except BERI/CHERI are 1000Hz. Well, Octeon is also 100Hz, due to the defaults, but it will be fine at 1000Hz, so maybe we need to attend to this as well. Arm !=v5 is also 1000Hz, so it should be changed... > I don't feel terribly strongly about this though. I've just been bitten > several times in the last week on a <15MHz FPGA forgetting to set HZ=100 > in config and figured I'd save others the trouble. ;-) > 15MHz FPGA? FreeBSD 1.0 barely ran on 25MHz i386 machines of the time.... How common are these beasts and how well does FreeBSD do on them. I assume these are early prototypes? I have no strong opinion on riscv, but do think mips and arm should change. Warner