From owner-svn-src-head@freebsd.org Sat Aug 8 11:48:13 2015 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 146CB9B63CE; Sat, 8 Aug 2015 11:48:13 +0000 (UTC) (envelope-from mav@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 04AD6189E; Sat, 8 Aug 2015 11:48:13 +0000 (UTC) (envelope-from mav@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.70]) by repo.freebsd.org (8.14.9/8.14.9) with ESMTP id t78BmCIK012234; Sat, 8 Aug 2015 11:48:12 GMT (envelope-from mav@FreeBSD.org) Received: (from mav@localhost) by repo.freebsd.org (8.14.9/8.14.9/Submit) id t78BmC3F012231; Sat, 8 Aug 2015 11:48:12 GMT (envelope-from mav@FreeBSD.org) Message-Id: <201508081148.t78BmC3F012231@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: mav set sender to mav@FreeBSD.org using -f From: Alexander Motin Date: Sat, 8 Aug 2015 11:48:12 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r286448 - in head/sys: dev/ata dev/ata/chipsets sys X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 08 Aug 2015 11:48:13 -0000 Author: mav Date: Sat Aug 8 11:48:11 2015 New Revision: 286448 URL: https://svnweb.freebsd.org/changeset/base/286448 Log: Disable 32-bit PIO for 6Gbit/s Intel SATA controllers. For some reason 32-bit PIO writes are not working on 6Gbit/s Intel SATA ports, while 16/32-bit PIO reads and 16-bit PIO writes are working fine. 3Gbit/s ports on the same controllers have no this problem. Workaround this by disabling 32-bit PIO for all Intel controllers that may have 6Gbit/s ports. It halves PIO performance from 6MB/s to 3MB/s, but who bother about speed of such rare and slow mode, which is also highly discouraged by SATA specifications? MFC after: 2 weeks Modified: head/sys/dev/ata/ata-all.c head/sys/dev/ata/chipsets/ata-intel.c head/sys/sys/ata.h Modified: head/sys/dev/ata/ata-all.c ============================================================================== --- head/sys/dev/ata/ata-all.c Sat Aug 8 11:22:45 2015 (r286447) +++ head/sys/dev/ata/ata-all.c Sat Aug 8 11:48:11 2015 (r286448) @@ -572,6 +572,7 @@ ata_mode2str(int mode) case ATA_UDMA6: return "UDMA133"; case ATA_SA150: return "SATA150"; case ATA_SA300: return "SATA300"; + case ATA_SA600: return "SATA600"; default: if (mode & ATA_DMA_MASK) return "BIOSDMA"; Modified: head/sys/dev/ata/chipsets/ata-intel.c ============================================================================== --- head/sys/dev/ata/chipsets/ata-intel.c Sat Aug 8 11:22:45 2015 (r286447) +++ head/sys/dev/ata/chipsets/ata-intel.c Sat Aug 8 11:48:11 2015 (r286448) @@ -155,34 +155,34 @@ ata_intel_probe(device_t dev) { ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, { ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, { ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, - { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, - { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, + { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Cougar Point" }, + { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Cougar Point" }, { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, - { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA300, "Patsburg" }, + { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA600, "Patsburg" }, { ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" }, - { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, - { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, + { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Panther Point" }, + { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Panther Point" }, { ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, { ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, - { ATA_AVOTON_S1, 0, INTEL_6CH, 0, ATA_SA300, "Avoton" }, - { ATA_AVOTON_S2, 0, INTEL_6CH, 0, ATA_SA300, "Avoton" }, + { ATA_AVOTON_S1, 0, INTEL_6CH, 0, ATA_SA600, "Avoton" }, + { ATA_AVOTON_S2, 0, INTEL_6CH, 0, ATA_SA600, "Avoton" }, { ATA_AVOTON_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" }, { ATA_AVOTON_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" }, - { ATA_LPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" }, - { ATA_LPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" }, - { ATA_LPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" }, - { ATA_LPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" }, - { ATA_WCPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Wildcat Point" }, - { ATA_WCPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Wildcat Point" }, - { ATA_WCPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Wildcat Point" }, - { ATA_WCPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Wildcat Point" }, - { ATA_WELLS_S1, 0, INTEL_6CH, 0, ATA_SA300, "Wellsburg" }, - { ATA_WELLS_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Wellsburg" }, - { ATA_WELLS_S3, 0, INTEL_6CH, 0, ATA_SA300, "Wellsburg" }, - { ATA_WELLS_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Wellsburg" }, - { ATA_LPTLP_S1, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point-LP" }, - { ATA_LPTLP_S2, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point-LP" }, + { ATA_LPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point" }, + { ATA_LPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point" }, + { ATA_LPT_S3, 0, INTEL_6CH2, 0, ATA_SA600, "Lynx Point" }, + { ATA_LPT_S4, 0, INTEL_6CH2, 0, ATA_SA600, "Lynx Point" }, + { ATA_WCPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Wildcat Point" }, + { ATA_WCPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Wildcat Point" }, + { ATA_WCPT_S3, 0, INTEL_6CH2, 0, ATA_SA600, "Wildcat Point" }, + { ATA_WCPT_S4, 0, INTEL_6CH2, 0, ATA_SA600, "Wildcat Point" }, + { ATA_WELLS_S1, 0, INTEL_6CH, 0, ATA_SA600, "Wellsburg" }, + { ATA_WELLS_S2, 0, INTEL_6CH2, 0, ATA_SA600, "Wellsburg" }, + { ATA_WELLS_S3, 0, INTEL_6CH, 0, ATA_SA600, "Wellsburg" }, + { ATA_WELLS_S4, 0, INTEL_6CH2, 0, ATA_SA600, "Wellsburg" }, + { ATA_LPTLP_S1, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point-LP" }, + { ATA_LPTLP_S2, 0, INTEL_6CH, 0, ATA_SA600, "Lynx Point-LP" }, { ATA_LPTLP_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" }, { ATA_LPTLP_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" }, { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, @@ -394,6 +394,8 @@ ata_intel_ch_attach(device_t dev) } } else ctlr->setmode = ata_intel_new_setmode; + if (ctlr->chip->max_dma >= ATA_SA600) + ch->flags |= ATA_USE_16BIT; } else if (ctlr->chip->chipid != ATA_ISCH) ch->flags |= ATA_CHECKS_CABLE; return (0); Modified: head/sys/sys/ata.h ============================================================================== --- head/sys/sys/ata.h Sat Aug 8 11:22:45 2015 (r286447) +++ head/sys/sys/ata.h Sat Aug 8 11:48:11 2015 (r286448) @@ -335,6 +335,7 @@ struct ata_params { #define ATA_UDMA6 0x46 #define ATA_SA150 0x47 #define ATA_SA300 0x48 +#define ATA_SA600 0x49 #define ATA_DMA_MAX 0x4f