From owner-svn-src-all@FreeBSD.ORG Fri Jan 29 05:36:53 2010 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 919C6106566C; Fri, 29 Jan 2010 05:36:53 +0000 (UTC) (envelope-from neelnatu@gmail.com) Received: from mail-pw0-f44.google.com (mail-pw0-f44.google.com [209.85.160.44]) by mx1.freebsd.org (Postfix) with ESMTP id 598EA8FC0C; Fri, 29 Jan 2010 05:36:53 +0000 (UTC) Received: by pwi15 with SMTP id 15so1135081pwi.3 for ; Thu, 28 Jan 2010 21:36:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=5k0cVmKv/pkkOw46oqpQWjanNNFKXxmNwTRSCyW3/Yw=; b=bgtcQCC+M4EyFNmTaqi54awnXj+ZY4tKGPYkSnCs5u4UjBx0UNaZf8SuOdGLquVtZb YOfIoMaWPUUggtJfvoZWpvKrQdb+VNdd+UV97U0GLbx1S5ZXTYqXQtkCPVUTrTPDYZSH aCemeKNH/53DuSOm2CjHICQa/RzFhR8+771DE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=TOALqBhGIu1Y00kd6QTa1wdKkisxZ2Swhr1+yS4I+t47cZER6xqvKNGHhAj/iVtpfO XcwsP3nkAFQv8YdZPjisYcwXCKDYsBwSeCKOkODFogOLMtj2DZHO5ErG1ME/rdvFzQ7s xDY+MLoXBrDyppCZD5wjrDK73+OSkVD7/4BRQ= MIME-Version: 1.0 Received: by 10.143.27.23 with SMTP id e23mr268212wfj.31.1264741863082; Thu, 28 Jan 2010 21:11:03 -0800 (PST) In-Reply-To: <201001290407.o0T47cC0046783@svn.freebsd.org> References: <201001290407.o0T47cC0046783@svn.freebsd.org> Date: Thu, 28 Jan 2010 21:11:03 -0800 Message-ID: From: Neel Natu To: Randall Stewart Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org Subject: Re: svn commit: r203151 - head/sys/mips/mips X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2010 05:36:53 -0000 Hi Randall, You should use restoreintr() instead of unconditionally enabling interrupts using enableintr(). Otherwise these functions may end up inadvertently enabling interrupts if they are called with interrupts disabled to begin with. best Neel On Thu, Jan 28, 2010 at 8:07 PM, Randall Stewart wrote: > Author: rrs > Date: Fri Jan 29 04:07:38 2010 > New Revision: 203151 > URL: http://svn.freebsd.org/changeset/base/203151 > > Log: > =A0For our memory re-mapping trick to work > =A0interrupts must be disabled through the > =A0page_zero's or copys etc. Note that the > =A0temporary mapping used by panic's may > =A0cause us pain since int's may not be disabled. > =A0When we get dumps working we may have to revist > =A0this. Note that with this fix the build got > =A0much much further.. until it hung on disk IO (I > =A0would imagine thats the rge/msgring driver acting > =A0up). > > Modified: > =A0head/sys/mips/mips/pmap.c > > Modified: head/sys/mips/mips/pmap.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D > --- head/sys/mips/mips/pmap.c =A0 Fri Jan 29 04:05:17 2010 =A0 =A0 =A0 = =A0(r203150) > +++ head/sys/mips/mips/pmap.c =A0 Fri Jan 29 04:07:38 2010 =A0 =A0 =A0 = =A0(r203151) > @@ -2101,14 +2101,20 @@ pmap_kenter_temporary(vm_paddr_t pa, int > =A0 =A0 =A0 =A0} else { > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0int cpu; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0struct local_sysmaps *sysm; > - > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* If this is used other than for dumps, we= may need to leave > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0* interrupts disasbled on return. If cra= sh dumps don't work when > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0* we get to this point, we might want to= consider this (leaving things > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0* disabled as a starting point ;-) > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0*/ > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 disableintr(); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cpu =3D PCPU_GET(cpuid); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm =3D &sysmap_lmem[cpu]; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Since this is for the debugger, no lock= s or any other fun */ > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->CMAP1 =3D mips_paddr_to_tlbpfn(pa) |= PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 pmap_TLB_update_kernel((vm_offset_t)sysm->C= ADDR1, sysm->CMAP1); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->valid1 =3D 1; > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 pmap_TLB_update_kernel((vm_offset_t)sysm->C= ADDR1, sysm->CMAP1); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0va =3D (vm_offset_t)sysm->CADDR1; > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 enableintr(); > =A0 =A0 =A0 =A0} > =A0 =A0 =A0 =A0return ((void *)va); > =A0} > @@ -2126,7 +2132,9 @@ pmap_kenter_temporary_free(vm_paddr_t pa > =A0 =A0 =A0 =A0cpu =3D PCPU_GET(cpuid); > =A0 =A0 =A0 =A0sysm =3D &sysmap_lmem[cpu]; > =A0 =A0 =A0 =A0if (sysm->valid1) { > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 disableintr(); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0pmap_TLB_invalidate_kernel((vm_offset_t)sy= sm->CADDR1); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 enableintr(); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->CMAP1 =3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->valid1 =3D 0; > =A0 =A0 =A0 =A0} > @@ -2272,11 +2280,13 @@ pmap_zero_page(vm_page_t m) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm =3D &sysmap_lmem[cpu]; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0PMAP_LGMEM_LOCK(sysm); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sched_pin(); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 disableintr(); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->CMAP1 =3D mips_paddr_to_tlbpfn(phys)= | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->valid1 =3D 1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0pmap_TLB_update_kernel((vm_offset_t)sysm->= CADDR1, sysm->CMAP1); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0bzero(sysm->CADDR1, PAGE_SIZE); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0pmap_TLB_invalidate_kernel((vm_offset_t)sy= sm->CADDR1); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 enableintr(); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->CMAP1 =3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->valid1 =3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sched_unpin(); > @@ -2326,12 +2336,14 @@ pmap_zero_page_area(vm_page_t m, int off > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cpu =3D PCPU_GET(cpuid); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm =3D &sysmap_lmem[cpu]; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0PMAP_LGMEM_LOCK(sysm); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 disableintr(); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sched_pin(); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->CMAP1 =3D mips_paddr_to_tlbpfn(phys)= | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 pmap_TLB_update_kernel((vm_offset_t)sysm->C= ADDR1, sysm->CMAP1); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->valid1 =3D 1; > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 pmap_TLB_update_kernel((vm_offset_t)sysm->C= ADDR1, sysm->CMAP1); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0bzero((char *)sysm->CADDR1 + off, size); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0pmap_TLB_invalidate_kernel((vm_offset_t)sy= sm->CADDR1); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 enableintr(); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->CMAP1 =3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->valid1 =3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sched_unpin(); > @@ -2365,12 +2377,14 @@ pmap_zero_page_idle(vm_page_t m) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cpu =3D PCPU_GET(cpuid); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm =3D &sysmap_lmem[cpu]; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0PMAP_LGMEM_LOCK(sysm); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 disableintr(); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sched_pin(); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->CMAP1 =3D mips_paddr_to_tlbpfn(phys)= | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 pmap_TLB_update_kernel((vm_offset_t)sysm->C= ADDR1, sysm->CMAP1); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->valid1 =3D 1; > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 pmap_TLB_update_kernel((vm_offset_t)sysm->C= ADDR1, sysm->CMAP1); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0bzero(sysm->CADDR1, PAGE_SIZE); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0pmap_TLB_invalidate_kernel((vm_offset_t)sy= sm->CADDR1); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 enableintr(); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->CMAP1 =3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->valid1 =3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sched_unpin(); > @@ -2441,6 +2455,7 @@ pmap_copy_page(vm_page_t src, vm_page_t > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm =3D &sysmap_lmem[cpu]= ; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0PMAP_LGMEM_LOCK(sysm); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sched_pin(); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 disableintr(); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (phy_src < MIPS_KSEG0_L= ARGEST_PHYS) { > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* one sid= e needs mapping - dest */ > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0va_src =3D= MIPS_PHYS_TO_CACHED(phy_src); > @@ -2476,6 +2491,7 @@ pmap_copy_page(vm_page_t src, vm_page_t > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->CMAP= 2 =3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sysm->vali= d2 =3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0} > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 enableintr(); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sched_unpin(); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0PMAP_LGMEM_UNLOCK(sysm); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0} >