From owner-svn-src-head@freebsd.org Thu Jun 14 05:43:47 2018 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id E524410018AD; Thu, 14 Jun 2018 05:43:46 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 9301E744D0; Thu, 14 Jun 2018 05:43:46 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 5AFAF243F7; Thu, 14 Jun 2018 05:43:46 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w5E5hkhc036520; Thu, 14 Jun 2018 05:43:46 GMT (envelope-from manu@FreeBSD.org) Received: (from manu@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w5E5hjS8036518; Thu, 14 Jun 2018 05:43:45 GMT (envelope-from manu@FreeBSD.org) Message-Id: <201806140543.w5E5hjS8036518@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: manu set sender to manu@FreeBSD.org using -f From: Emmanuel Vadot Date: Thu, 14 Jun 2018 05:43:45 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r335108 - head/sys/arm64/rockchip/clk X-SVN-Group: head X-SVN-Commit-Author: manu X-SVN-Commit-Paths: head/sys/arm64/rockchip/clk X-SVN-Commit-Revision: 335108 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jun 2018 05:43:47 -0000 Author: manu Date: Thu Jun 14 05:43:45 2018 New Revision: 335108 URL: https://svnweb.freebsd.org/changeset/base/335108 Log: rk_pll: Add support for mode RockChip PLL have two modes controlled by a register, a "slow mode" (the default one) where the frequency is derived from the 24Mhz oscillator on the board, and a "normal" one when the pll take it's input from the real PLL output. Default the mode to normal for all the PLLs. Modified: head/sys/arm64/rockchip/clk/rk3328_cru.c head/sys/arm64/rockchip/clk/rk_clk_pll.c head/sys/arm64/rockchip/clk/rk_clk_pll.h Modified: head/sys/arm64/rockchip/clk/rk3328_cru.c ============================================================================== --- head/sys/arm64/rockchip/clk/rk3328_cru.c Thu Jun 14 05:41:16 2018 (r335107) +++ head/sys/arm64/rockchip/clk/rk3328_cru.c Thu Jun 14 05:43:45 2018 (r335108) @@ -512,6 +512,8 @@ static struct rk_clk_pll_def apll = { .base_offset = 0x00, .gate_offset = 0x200, .gate_shift = 0, + .mode_reg = 0x80, + .mode_val = 0x1, .flags = RK_CLK_PLL_HAVE_GATE, .frac_rates = rk3328_pll_frac_rates, }; @@ -526,6 +528,8 @@ static struct rk_clk_pll_def dpll = { .base_offset = 0x20, .gate_offset = 0x200, .gate_shift = 1, + .mode_reg = 0x80, + .mode_val = 0x8, .flags = RK_CLK_PLL_HAVE_GATE, }; @@ -537,6 +541,8 @@ static struct rk_clk_pll_def cpll = { .parent_cnt = nitems(pll_parents), }, .base_offset = 0x40, + .mode_reg = 0x80, + .mode_val = 0x80, .rates = rk3328_pll_rates, }; @@ -550,6 +556,8 @@ static struct rk_clk_pll_def gpll = { .base_offset = 0x60, .gate_offset = 0x200, .gate_shift = 2, + .mode_reg = 0x80, + .mode_val = 0x800, .flags = RK_CLK_PLL_HAVE_GATE, .frac_rates = rk3328_pll_frac_rates, }; @@ -564,6 +572,8 @@ static struct rk_clk_pll_def npll = { .base_offset = 0xa0, .gate_offset = 0x200, .gate_shift = 12, + .mode_reg = 0x80, + .mode_val = 0x2, .flags = RK_CLK_PLL_HAVE_GATE, .rates = rk3328_pll_rates, }; Modified: head/sys/arm64/rockchip/clk/rk_clk_pll.c ============================================================================== --- head/sys/arm64/rockchip/clk/rk_clk_pll.c Thu Jun 14 05:41:16 2018 (r335107) +++ head/sys/arm64/rockchip/clk/rk_clk_pll.c Thu Jun 14 05:43:45 2018 (r335108) @@ -47,6 +47,9 @@ struct rk_clk_pll_sc { uint32_t gate_offset; uint32_t gate_shift; + uint32_t mode_reg; + uint32_t mode_val; + uint32_t flags; struct rk_clk_pll_rate *rates; @@ -221,6 +224,11 @@ rk_clk_pll_set_freq(struct clknode *clk, uint64_t fpar reg |= rates->frac << RK_CLK_PLL_FRAC_SHIFT; WRITE4(clk, sc->base_offset + 0x8, reg); + /* Setting to normal mode */ + READ4(clk, sc->mode_reg, ®); + reg |= sc->mode_val << 16 | sc->mode_val; + WRITE4(clk, sc->mode_reg, reg); + /* Reading lock */ for (timeout = 1000; timeout; timeout--) { READ4(clk, sc->base_offset + 0x4, ®); @@ -263,6 +271,8 @@ rk_clk_pll_register(struct clkdom *clkdom, struct rk_c sc->base_offset = clkdef->base_offset; sc->gate_offset = clkdef->gate_offset; sc->gate_shift = clkdef->gate_shift; + sc->mode_reg = clkdef->mode_reg; + sc->mode_val = clkdef->mode_val; sc->flags = clkdef->flags; sc->rates = clkdef->rates; sc->frac_rates = clkdef->frac_rates; Modified: head/sys/arm64/rockchip/clk/rk_clk_pll.h ============================================================================== --- head/sys/arm64/rockchip/clk/rk_clk_pll.h Thu Jun 14 05:41:16 2018 (r335107) +++ head/sys/arm64/rockchip/clk/rk_clk_pll.h Thu Jun 14 05:43:45 2018 (r335108) @@ -50,6 +50,9 @@ struct rk_clk_pll_def { uint32_t gate_offset; uint32_t gate_shift; + uint32_t mode_reg; + uint32_t mode_val; + uint32_t flags; struct rk_clk_pll_rate *rates;