Date: Thu, 19 Mar 2020 03:19:58 +0000 (UTC) From: Yuri Victorovich <yuri@FreeBSD.org> To: ports-committers@freebsd.org, svn-ports-all@freebsd.org, svn-ports-head@freebsd.org Subject: svn commit: r528682 - in head/cad: . netgen-lvs netgen-lvs/files Message-ID: <202003190319.02J3JwtB035347@repo.freebsd.org>
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Author: yuri Date: Thu Mar 19 03:19:57 2020 New Revision: 528682 URL: https://svnweb.freebsd.org/changeset/ports/528682 Log: New port: cad/netgen-lvs: Tool for comparing netlists (a process known as LVS) Added: head/cad/netgen-lvs/ head/cad/netgen-lvs/Makefile (contents, props changed) head/cad/netgen-lvs/distinfo (contents, props changed) head/cad/netgen-lvs/files/ head/cad/netgen-lvs/files/patch-python_Makefile (contents, props changed) head/cad/netgen-lvs/pkg-descr (contents, props changed) head/cad/netgen-lvs/pkg-plist (contents, props changed) Modified: head/cad/Makefile Modified: head/cad/Makefile ============================================================================== --- head/cad/Makefile Thu Mar 19 01:24:15 2020 (r528681) +++ head/cad/Makefile Thu Mar 19 03:19:57 2020 (r528682) @@ -71,6 +71,7 @@ SUBDIR += magic SUBDIR += meshdev SUBDIR += netgen + SUBDIR += netgen-lvs SUBDIR += ngspice_rework SUBDIR += nvc SUBDIR += opencascade Added: head/cad/netgen-lvs/Makefile ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/cad/netgen-lvs/Makefile Thu Mar 19 03:19:57 2020 (r528682) @@ -0,0 +1,25 @@ +# $FreeBSD$ + +PORTNAME= netgen +DISTVERSION= 1.5.144 +CATEGORIES= cad +MASTER_SITES= http://opencircuitdesign.com/netgen/archive/ +PKGNAMESUFFIX= -lvs + +MAINTAINER= yuri@FreeBSD.org +COMMENT= Tool for comparing netlists (a process known as LVS) + +LICENSE= GPLv1 +LICENSE_FILE= ${WRKSRC}/Copying + +USES= gmake python tar:tgz + +GNU_CONFIGURE= yes + +post-patch: + @${REINPLACE_CMD} -e 's|^#!/bin/env python3$$|#!${PYTHON_CMD}|' ${WRKSRC}/python/*.py + +post-stage: + @${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/* + +.include <bsd.port.mk> Added: head/cad/netgen-lvs/distinfo ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/cad/netgen-lvs/distinfo Thu Mar 19 03:19:57 2020 (r528682) @@ -0,0 +1,3 @@ +TIMESTAMP = 1584583774 +SHA256 (netgen-1.5.144.tgz) = 209b801d8c8051f60cf0845e564a5b200791b6a955d96f64d1b4d959133d9aa9 +SIZE (netgen-1.5.144.tgz) = 522869 Added: head/cad/netgen-lvs/files/patch-python_Makefile ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/cad/netgen-lvs/files/patch-python_Makefile Thu Mar 19 03:19:57 2020 (r528682) @@ -0,0 +1,12 @@ +--- python/Makefile.orig 2020-02-24 21:24:48 UTC ++++ python/Makefile +@@ -46,6 +46,9 @@ $(DESTDIR)${INSTALL_PYDIR}/lvs_help.txt: lvs_help.txt + + install: install-tcl + ++$(DESTDIR)${INSTALL_PYDIR}: ++ mkdir -p $(DESTDIR)${INSTALL_PYDIR} ++ + install-tcl: $(DESTDIR)${INSTALL_PYDIR} $(DESTDIR)${INSTALL_PYDIR}/consoletext.py \ + $(DESTDIR)${INSTALL_PYDIR}/helpwindow.py $(DESTDIR)${INSTALL_PYDIR}/lvs_manager.py \ + $(DESTDIR)${INSTALL_PYDIR}/treeviewsplit.py $(DESTDIR)${INSTALL_PYDIR}/tksimpledialog.py \ Added: head/cad/netgen-lvs/pkg-descr ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/cad/netgen-lvs/pkg-descr Thu Mar 19 03:19:57 2020 (r528682) @@ -0,0 +1,12 @@ +Netgen is a tool for comparing netlists, a process known as LVS, which stands +for "Layout vs. Schematic". This is an important step in the integrated circuit +design flow, ensuring that the geometry that has been laid out matches the +expected circuit. Very small circuits can bypass this step by confirming circuit +operation through extraction and simulation. Very large digital circuits are +usually generated by tools from high-level descriptions, using compilers that +ensure the correct layout geometry. The greatest need for LVS is in large analog +or mixed-signal circuits that cannot be simulated in reasonable time. Even for +small circuits, LVS can be done much faster than simulation, and provides +feedback that makes it easier to find an error than does a simulation. + +WWW: http://opencircuitdesign.com/netgen/ Added: head/cad/netgen-lvs/pkg-plist ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/cad/netgen-lvs/pkg-plist Thu Mar 19 03:19:57 2020 (r528682) @@ -0,0 +1,17 @@ +bin/inetcomp +bin/netcomp +bin/netgen +bin/ntk2adl +bin/ntk2xnf +lib/netgen/doc/netgen.doc +lib/netgen/ntk2adl.sh +lib/netgen/python/consoletext.py +lib/netgen/python/helpwindow.py +lib/netgen/python/lvs_help.txt +lib/netgen/python/lvs_manager.py +lib/netgen/python/tksimpledialog.py +lib/netgen/python/tooltip.py +lib/netgen/python/treeviewsplit.py +lib/netgen/spice +lib/netgen/spice.bot +lib/netgen/spice.top
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