Date: Thu, 7 Nov 2013 07:07:11 GMT From: John Wehle <john@feith.com> To: freebsd-gnats-submit@FreeBSD.org Subject: arm/183740: mutex on some arm hardware requires dcache enabled Message-ID: <201311070707.rA777BvG084136@oldred.freebsd.org> Resent-Message-ID: <201311070710.rA77A0x0024495@freefall.freebsd.org>
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>Number: 183740 >Category: arm >Synopsis: mutex on some arm hardware requires dcache enabled >Confidential: no >Severity: non-critical >Priority: low >Responsible: freebsd-arm >State: open >Quarter: >Keywords: >Date-Required: >Class: sw-bug >Submitter-Id: current-users >Arrival-Date: Thu Nov 07 07:10:00 UTC 2013 >Closed-Date: >Last-Modified: >Originator: John Wehle >Release: FreeBSD svn 257205 >Organization: Personal >Environment: Not Yet >Description: In my spare time I'm working on bringing FreeBSD up on amlogic based arm processors. While working through various bootstrap issues I got to the point where initarm calls pmap_bootstrap only to have it splat. What happens is pmap_bootstrap calls pmap_extract which does PMAP_LOCK(pmap). This trys to acquire a mutex which invokes atomics that use ldrex / strex. The ARM documentation at: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0464d/CHDIBJGE.html notes that the L1 memory system has an internal exclusive monitor which handles ldrex / strex accesses. The README at: https://github.com/dwelch67/raspberrypi/tree/master/extest has a nice write up which explains some of the wrinkles regarding hardware and ldrex / strex. The attached patch enables the dcache and suffices to get me through initarm into mi_startup (I'm not to a console login yet ... however I'm significantly further along). -- John >How-To-Repeat: >Fix: Enable the dcache prior to using a mutex. Patch attached with submission follows: --- sys/arm/arm/machdep.c.ORIGINAL 2013-10-27 01:15:39.000000000 -0400 +++ sys/arm/arm/machdep.c 2013-11-07 01:43:01.000000000 -0500 @@ -1481,6 +1483,12 @@ initarm(struct arm_boot_params *abp) */ cpu_idcache_wbinv_all(); + /* + * Atomics invoked by mutex use ldrex / strex which on some + * hardware requires the L1 cache. + */ + cpu_control(CPU_CONTROL_DC_ENABLE, CPU_CONTROL_DC_ENABLE); + /* Set stack for exception handlers */ data_abort_handler_address = (u_int)data_abort_handler; prefetch_abort_handler_address = (u_int)prefetch_abort_handler; >Release-Note: >Audit-Trail: >Unformatted:
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