From owner-freebsd-hackers@freebsd.org Sat Oct 21 14:09:56 2017 Return-Path: Delivered-To: freebsd-hackers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 01B4FE2BBFE for ; Sat, 21 Oct 2017 14:09:56 +0000 (UTC) (envelope-from Hartmut.Brandt@dlr.de) Received: from mailman.ysv.freebsd.org (mailman.ysv.freebsd.org [IPv6:2001:1900:2254:206a::50:5]) by mx1.freebsd.org (Postfix) with ESMTP id DF74D84F38 for ; Sat, 21 Oct 2017 14:09:55 +0000 (UTC) (envelope-from Hartmut.Brandt@dlr.de) Received: by mailman.ysv.freebsd.org (Postfix) id DB92DE2BBFD; Sat, 21 Oct 2017 14:09:55 +0000 (UTC) Delivered-To: hackers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id DB25BE2BBFC for ; Sat, 21 Oct 2017 14:09:55 +0000 (UTC) (envelope-from Hartmut.Brandt@dlr.de) Received: from mailhost.dlr.de (mailhost.dlr.de [129.247.252.33]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mailhost.dlr.de", Issuer "DLR CA - G02" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 714C784F37 for ; Sat, 21 Oct 2017 14:09:54 +0000 (UTC) (envelope-from Hartmut.Brandt@dlr.de) Received: from DLREXHUB02.intra.dlr.de (172.21.152.140) by mailhost.dlr.de (172.21.163.101) with Microsoft SMTP Server (TLS) id 14.3.361.1; Sat, 21 Oct 2017 16:08:34 +0200 Received: from KNOP-BEAGLE.kn.op.dlr.de (129.247.178.136) by smtp.dlr.de (172.21.152.151) with Microsoft SMTP Server (TLS) id 14.3.361.1; Sat, 21 Oct 2017 16:08:41 +0200 Date: Sat, 21 Oct 2017 16:08:57 +0200 From: Hartmut Brandt X-X-Sender: brandt_h@KNOP-BEAGLE.kn.op.dlr.de To: Subject: PCIe transaction size Message-ID: User-Agent: Alpine 2.20 (BSF 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="US-ASCII" X-TM-AS-Product-Ver: SMEX-11.0.0.4283-8.100.1062-23408.007 X-TM-AS-Result: No-1.970300-5.000000-31 X-TM-AS-MatchedID: 706891-711871-860275-708497-707136-709584-705882-701837-7 05706-701775-700398-148004-148050-10007-41000-42000-42003-63 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 21 Oct 2017 14:09:56 -0000 Hi all, I'm designing a FPGA board that has memory that is accessible via the PCIe bus from FreeBSD. I observed, that the host always splits the memory transactions on 8 byte boundaries. So reading or storing an 128-bit integer generates two transactions, if the integer is unaligned even four. Is there a way to get the CPU or chipset or whoever produces the transactions to make larger transactions? I found an Intel paper that seems to talk about this (How to Implement a 64B PCIe Burst Transfer or Intel Architecture) but I've no idea how to do what they write on FreeBSD :-). Any help? harti