Date: Thu, 14 Jun 2018 05:46:57 +0000 (UTC) From: Emmanuel Vadot <manu@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r335109 - head/sys/arm64/rockchip/clk Message-ID: <201806140546.w5E5kvDY036710@repo.freebsd.org>
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Author: manu Date: Thu Jun 14 05:46:57 2018 New Revision: 335109 URL: https://svnweb.freebsd.org/changeset/base/335109 Log: rk_armclk: Add the write mask to the register mux value This was omitted in r334112 and r334996 which cause the PLL to not correctly reparent, leaving the armclk to be derived from the APLL instead of the NPLL. The arm core clock is now correctly set to 600Mhz via the assigned-clock present in the DTB. Modified: head/sys/arm64/rockchip/clk/rk_clk_armclk.c Modified: head/sys/arm64/rockchip/clk/rk_clk_armclk.c ============================================================================== --- head/sys/arm64/rockchip/clk/rk_clk_armclk.c Thu Jun 14 05:43:45 2018 (r335108) +++ head/sys/arm64/rockchip/clk/rk_clk_armclk.c Thu Jun 14 05:46:57 2018 (r335109) @@ -105,7 +105,7 @@ rk_clk_armclk_set_mux(struct clknode *clk, int index) DEVICE_LOCK(clk); READ4(clk, sc->muxdiv_offset, &val); val &= ~(sc->mux_mask >> sc->mux_shift); - val |= index << sc->mux_shift; + val |= index << sc->mux_shift | RK_ARMCLK_WRITE_MASK; WRITE4(clk, sc->muxdiv_offset, val); DEVICE_UNLOCK(clk);
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