Date: Tue, 25 Apr 2000 19:10:19 +0000 (GMT) From: Terry Lambert <tlambert@primenet.com> To: mihara@prd.fc.nec.co.jp (Osamu MIHARA) Cc: gallatin@cs.duke.edu, freebsd-smp@FreeBSD.ORG Subject: Re: I/O APIC Message-ID: <200004251910.MAA05939@usr05.primenet.com> In-Reply-To: <868zy9v9cs.wl@oz.prd.fc.nec.co.jp> from "Osamu MIHARA" at Apr 20, 2000 10:39:47 AM
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Not to chime in late here... > > When installing Solaris/x86 on one of our PowerEdge 2400s (SMP > > capable, 2 I/O APICs, 1 CPU), I noticed that it uses the I/O APICs for > > interrupts rather than the normal isa irq x. Is there an advantage to > > this? > > One advantage is that multiple I/O-APICs can handle more interrupts > than traditional PIC. If you use PIC, it can handles only 16 > interrupts at most, and you may need share a interrupt for some > devices. With multiple IO-APICs, you don't need to share interrupts, > and it does not pay for overheads of interrupt sharing, resulting in > better I/O throughput, even with single CPU. Another advantage, according to the Intel MultiProcessing spec., version 1.4, is that it allows you to run in "virtual wire mode". In "virtual wire mode", interrupt processing is symmetric between processors. In practice, you really want to split interrupt processing in virtual wire mode, but non-symmetrically, using IPI's to signal the "correct" processor, with the net effect that you "lock" interrupt handling for each of the 4 cards to each one of 4 processors. This is the method NT used on its 4 ethernet card, 4 processor machine in the infamous NetCraft and Ziff-Davis tests, where NT was able to handily beat Linux, running with the same hardware configuration. Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers. To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-smp" in the body of the message
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