From nobody Sat Jun 17 16:19:59 2023 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Qk1TD1ZjPz4fn0q; Sat, 17 Jun 2023 16:20:00 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Qk1TD18whz4JJC; Sat, 17 Jun 2023 16:20:00 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1687018800; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=ye/FPOFOGlEmw1NpSxYFxFmV5aCtkCKYTFUgKYAYMlw=; b=oyWyeGVO7XtEjQfaQvkvaAZxpLvcpxGjnQUI7VUgJv9YJ+Y7tpsvpGudNcnsk5D7DZJ/3R Hx2/GG+tKwrkNlvQvyQfh6k1Fptg9LDRb+rlQLmY2ku3bPUaJaQg5GgVXt7dwZ8vtLDrke JbfS2p1d61H9LEOKnghhjExrzEAprUx0hFMc4wS9ioYk4NP3UnUlmidgQe16fI4qze/b2u lrDt0Xnp3KiXdfKvAREEhLiX44nUiATwjH7QwHkdqcsbzAqH+bAgOuHC3JisD+Aa7f+jLI JGADrJlBEvSxjmq7rpSNt45TmW6Aa9JhERv06t9HDGd8J37+zdt7oDCFZZFwzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1687018800; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=ye/FPOFOGlEmw1NpSxYFxFmV5aCtkCKYTFUgKYAYMlw=; b=cyLmTIwWY05ACMGRXrYC26W6/YMLvxO2re4N9UmXVJi3GFOkprwqJukXV433zGpO7hHZLm sG9tA8UQ456mh7yl2ilDbzJ7E4dCFhzzs0Bq4ZOOsQ1+m6oQBa9JoE7gwSFm8WeKcVOuRu 1yD6srI2zDPPWB/Q8AnfbxGNnaRVBmgEyNg+f91yXWFf4NbdrsLNLZnBj9TmG+a0OT1tbY RNr9EuXhoyvP72zYV8nAtR5lJa/t//HBH+f1Mg1fIH+4Am1Tq5yVto5uBxoT4zuFukTpt6 O+mZRdQJr8Nkw5Lo3Va5lYQCneWv6tJ5roYU8Nn9F7G083ihXOVy6kGHafw5uQ== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1687018800; a=rsa-sha256; cv=none; b=XbuPTu1b2j0OrOY4UHK/esL/2zbowTu+053/OufDlkn+Tqp7C57+nI/EWHwN7A4TDKllR6 t//Fku1WIHbc38Db6DGok8J9kfmtlmoikI5vwA8ax48G4MjiYK7wEQavuGxlaXxifBi+nN PUKL8T3uWCamjW8OSOiMku+KLR0OuKZz2n/S6ynF4LafwlIyPbCtkOBdGo/UEFoqxw5x27 siFj9JZ5XNot95bmKFO1FXMPxpFTtpwXNT547ANlvZUDQ6hIWu8o40BmGiqhLc6ofBRVp0 lqZ7swp6w1uxS42VB3BJsHNM0+DbmHLIFwRYnTev0pFKxPJ7c80tm48bIzbsbA== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4Qk1TC6qnvz1Fy8; Sat, 17 Jun 2023 16:19:59 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 35HGJxPs000681; Sat, 17 Jun 2023 16:19:59 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 35HGJxP7000680; Sat, 17 Jun 2023 16:19:59 GMT (envelope-from git) Date: Sat, 17 Jun 2023 16:19:59 GMT Message-Id: <202306171619.35HGJxP7000680@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Mitchell Horne Subject: git: 9aef25d2686b - main - arm64/disassem.c: Add shifted register definitions with ror List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mhorne X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 9aef25d2686b9e7fb9cb700d63291338e8e30bb6 Auto-Submitted: auto-generated X-ThisMailContainsUnwantedMimeParts: N The branch main has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=9aef25d2686b9e7fb9cb700d63291338e8e30bb6 commit 9aef25d2686b9e7fb9cb700d63291338e8e30bb6 Author: Mykola Hohsadze AuthorDate: 2023-06-17 15:31:25 +0000 Commit: Mitchell Horne CommitDate: 2023-06-17 16:19:37 +0000 arm64/disassem.c: Add shifted register definitions with ror Add disassembly support for the following shifted register instructions: * mvn * orn * orr * and * ands * bic * bics * eon * eor * tst According to Arm64 documenation, operational pseuducode of shifted register instruction must return `UNDEFINED` if shift type is `RESERVED` ('11'). Hence, removed "rsv" from `shift_2` array and add "ror". In case of shift type is 3 and this type is `RESERVED`, we will return `undefined`. Reviewed by: mhorne MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D40386 --- sys/arm64/arm64/disassem.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/sys/arm64/arm64/disassem.c b/sys/arm64/arm64/disassem.c index f1a4f9206c1b..5dc0bf5100ef 100644 --- a/sys/arm64/arm64/disassem.c +++ b/sys/arm64/arm64/disassem.c @@ -53,6 +53,7 @@ __FBSDID("$FreeBSD$"); #define OP_RT_SP (1UL << 8) /* Use sp for RT otherwise xzr */ #define OP_RN_SP (1UL << 9) /* Use sp for RN otherwise xzr */ #define OP_RM_SP (1UL << 10) /* Use sp for RM otherwise xzr */ +#define OP_SHIFT_ROR (1UL << 11) /* Use ror shift type */ static const char *w_reg[] = { "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", @@ -69,7 +70,7 @@ static const char *x_reg[] = { }; static const char *shift_2[] = { - "lsl", "lsr", "asr", "rsv" + "lsl", "lsr", "asr", "ror" }; /* @@ -232,6 +233,28 @@ static struct arm64_insn arm64_i[] = { TYPE_01, 0 }, /* negs shifted register */ { "subs", "SF(1)|1101011|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)", TYPE_01, 0 }, /* subs shifted register */ + { "mvn", "SF(1)|0101010|SHIFT(2)|1|RM(5)|IMM(6)|11111|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* mvn shifted register */ + { "orn", "SF(1)|0101010|SHIFT(2)|1|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* orn shifted register */ + { "mov", "SF(1)|0101010000|RM(5)|000000|11111|RD(5)", + TYPE_01, 0 }, /* mov register */ + { "orr", "SF(1)|0101010|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* orr shifted register */ + { "and", "SF(1)|0001010|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* and shifted register */ + { "tst", "SF(1)|1101010|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|11111", + TYPE_01, OP_SHIFT_ROR }, /* tst shifted register */ + { "ands", "SF(1)|1101010|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* ands shifted register */ + { "bic", "SF(1)|0001010|SHIFT(2)|1|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* bic shifted register */ + { "bics", "SF(1)|1101010|SHIFT(2)|1|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* bics shifted register */ + { "eon", "SF(1)|1001010|SHIFT(2)|1|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* eon shifted register */ + { "eor", "SF(1)|1001010|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, OP_SHIFT_ROR }, /* eor shifted register */ { NULL, NULL } }; @@ -420,6 +443,8 @@ disasm(const struct disasm_interface *di, vm_offset_t loc, int altfmt) int pre; /* Indicate if x31 register should be printed as sp or xzr */ int rm_sp, rt_sp, rd_sp, rn_sp; + /* Indicate if shift type ror is supported */ + bool has_shift_ror; /* Initialize defaults, all are 0 except SF indicating 64bit access */ shift = rd = rm = rn = imm = idx = option = amount = scale = 0; @@ -464,6 +489,8 @@ disasm(const struct disasm_interface *di, vm_offset_t loc, int altfmt) rd_sp = i_ptr->special_ops & OP_RD_SP; rn_sp = i_ptr->special_ops & OP_RN_SP; + has_shift_ror = i_ptr->special_ops & OP_SHIFT_ROR; + /* Print opcode by type */ switch (i_ptr->type) { case TYPE_01: @@ -479,6 +506,13 @@ disasm(const struct disasm_interface *di, vm_offset_t loc, int altfmt) rm_absent = arm64_disasm_read_token(i_ptr, insn, "RM", &rm); arm64_disasm_read_token(i_ptr, insn, "SHIFT", &shift); + /* + * if shift type is RESERVED for shifted register instruction, + * print undefined + */ + if (shift == 3 && !has_shift_ror) + goto undefined; + di->di_printf("%s\t", i_ptr->name); /*