Date: Thu, 12 Jun 2008 17:22:22 GMT From: Przemek Witaszczyk <vi0@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 143378 for review Message-ID: <200806121722.m5CHMMap083981@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=143378 Change 143378 by vi0@vi0_gilgamesh.semihalf.com on 2008/06/12 17:22:02 Bootable code, merged with A. Turner's patch (after minor adjustments). Affected files ... .. //depot/projects/soc2008/vi0/efika/sys/conf/files.powerpc#3 edit .. //depot/projects/soc2008/vi0/efika/sys/conf/files.powerpc.orig#1 add .. //depot/projects/soc2008/vi0/efika/sys/dev/ofw/openfirm.c#2 edit .. //depot/projects/soc2008/vi0/efika/sys/dev/ofw/openfirm.c.orig#1 add .. //depot/projects/soc2008/vi0/efika/sys/powerpc/aim/locore.S#2 edit .. //depot/projects/soc2008/vi0/efika/sys/powerpc/aim/locore.S.orig#1 add .. //depot/projects/soc2008/vi0/efika/sys/powerpc/aim/machdep.c#3 edit .. //depot/projects/soc2008/vi0/efika/sys/powerpc/aim/machdep.c.orig#1 add .. //depot/projects/soc2008/vi0/efika/sys/powerpc/aim/mmu_oea.c#3 edit .. //depot/projects/soc2008/vi0/efika/sys/powerpc/aim/mmu_oea.c.orig#1 add .. //depot/projects/soc2008/vi0/efika/sys/powerpc/aim/ofw_oea.S#1 add .. //depot/projects/soc2008/vi0/efika/sys/powerpc/aim/ofwreal.S#1 add .. //depot/projects/soc2008/vi0/efika/sys/powerpc/aim/trap_subr.S#2 edit .. //depot/projects/soc2008/vi0/efika/sys/powerpc/aim/trap_subr.S.orig#1 add .. //depot/projects/soc2008/vi0/efika/sys/powerpc/include/psl.h#2 edit .. //depot/projects/soc2008/vi0/efika/sys/powerpc/include/psl.h.orig#1 add Differences ... ==== //depot/projects/soc2008/vi0/efika/sys/conf/files.powerpc#3 (text+ko) ==== @@ -72,6 +72,8 @@ powerpc/aim/mp_cpudep.c optional aim smp powerpc/aim/nexus.c optional aim powerpc/aim/ofw_machdep.c optional aim +powerpc/aim/ofw_oea.S optional aim +powerpc/aim/ofwreal.S optional aim powerpc/aim/ofwmagic.S optional aim powerpc/aim/swtch.S optional aim powerpc/aim/trap.c optional aim ==== //depot/projects/soc2008/vi0/efika/sys/dev/ofw/openfirm.c#2 (text+ko) ==== @@ -71,6 +71,10 @@ static ihandle_t stdout; +char *OF_buf; + +void ofw_stack(void); + /* Initialiser */ void @@ -599,12 +603,15 @@ 1, }; + ofw_stack(); args.instance = instance; - args.addr = (cell_t)addr; + args.addr = (cell_t)OF_buf; args.len = len; if (openfirmware(&args) == -1) return (-1); + bcopy(OF_buf, addr, len); + return (args.actual); } @@ -626,9 +633,12 @@ 1, }; + ofw_stack(); args.instance = instance; - args.addr = (cell_t)addr; + bcopy(addr, OF_buf, len); + args.addr = (cell_t)OF_buf; args.len = len; + if (openfirmware(&args) == -1) return (-1); return (args.actual); ==== //depot/projects/soc2008/vi0/efika/sys/powerpc/aim/locore.S#2 (text+ko) ==== @@ -89,6 +89,9 @@ GLOBAL(esym) .long 0 /* end of symbol table */ +GLOBAL(firmstk) + .space PAGE_SIZE,8 + GLOBAL(ofmsr) .long 0, 0, 0, 0, 0 /* msr/sprg0-3 used in Open Firmware */ @@ -126,14 +129,8 @@ .text .globl __start __start: -#ifdef FIRMWORKSBUGS - mfmsr 0 - andi. 0,0,PSL_IR|PSL_DR - beq 1f - bl ofwr_init -1: -#endif + li 8,0 li 9,0x100 mtctr 9 ==== //depot/projects/soc2008/vi0/efika/sys/powerpc/aim/machdep.c#3 (text+ko) ==== @@ -239,6 +239,9 @@ extern void *extint, *extsize; extern void *dblow, *dbsize; extern void *vectrap, *vectrapsize; +extern void *imisstrap, *imisssize; +extern void *dlmisstrap, *dlmisssize; +extern void *dsmisstrap, *dsmisssize; u_int powerpc_init(u_int startkernel, u_int endkernel, u_int basekernel, void *mdp) @@ -332,6 +335,9 @@ bcopy(&trapcode, (void *)EXC_SC, (size_t)&trapsize); bcopy(&trapcode, (void *)EXC_TRC, (size_t)&trapsize); bcopy(&trapcode, (void *)EXC_FPA, (size_t)&trapsize); + bcopy(&imisstrap, (void *)EXC_IMISS, (size_t)&imisssize); + bcopy(&dlmisstrap, (void *)EXC_DLMISS, (size_t)&dlmisssize); + bcopy(&dsmisstrap, (void *)EXC_DSMISS, (size_t)&dsmisssize); bcopy(&vectrap, (void *)EXC_VEC, (size_t)&vectrapsize); bcopy(&trapcode, (void *)EXC_VECAST, (size_t)&trapsize); bcopy(&trapcode, (void *)EXC_THRM, (size_t)&trapsize); ==== //depot/projects/soc2008/vi0/efika/sys/powerpc/aim/mmu_oea.c#3 (text+ko) ==== @@ -661,6 +661,8 @@ trcp[0] = 0x1007; } +extern char *OF_buf; + void moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) { @@ -898,6 +900,8 @@ kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; kernel_pmap->pm_active = ~0; + OF_buf = (char *)moea_bootstrap_alloc(PAGE_SIZE, 0); + pmap_cpu_bootstrap(trace, 0); pmap_bootstrapped++; ==== //depot/projects/soc2008/vi0/efika/sys/powerpc/aim/trap_subr.S#2 (text+ko) ==== @@ -330,6 +330,209 @@ bla s_trap /* LR & 0xff00 is exception # */ CNAME(alisize) = .-CNAME(alitrap) + + /* + * It's G2 specific. Instuction TLB miss. + */ + .globl CNAME(imisstrap),CNAME(imisssize) +CNAME(imisstrap): + mfspr %r2, SPR_HASH1 /* get first pointer */ + addi %r1, 0, 8 /* load 8 for counter */ + mfctr %r0 /* save counter */ + mfspr %r3, SPR_ICMP /* get first compare value */ + addi %r2, %r2, -8 /* pre dec the pointer */ +im0: + mtctr %r1 /* load counter */ +im1: + lwzu %r1, 8(%r2) /* get next pte */ + cmp 0, %r1, %r3 /* see if found pte */ + bdnzf 2, im1 /* dec count br if cmp ne and if + * count not zero */ + bne instr_sec_hash /* if not found set up second hash + * or exit */ + lwz %r1, +4(%r2) /* load tlb entry lower-word */ + andi. %r3, %r1, 8 /* check G bit */ + bne do_isi_prot /* if guarded, take an ISI */ + mtctr %r0 /* restore counter */ + mfspr %r0, SPR_IMISS /* get the miss address for the tlbli */ + mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ + mtcrf 0x80, %r3 /* restore CR0 */ + mtspr SPR_RPA, %r1 /* set the pte */ + ori %r1, %r1, 0x100 /* set reference bit */ + srwi %r1, %r1, 8 /* get byte 7 of pte */ + tlbli %r0 /* load the itlb */ + stb %r1, +6(%r2) /* update page table */ + rfi /* return to executing program */ + +instr_sec_hash: + andi. %r1, %r3, 0x0040 /* see if we have done second hash */ + bne do_isi /* if so, go to ISI interrupt */ + mfspr %r2, SPR_HASH2 /* get the second pointer */ + ori %r3, %r3, 0x0040 /* change the compare value */ + addi %r1, %r0, 8 /* load 8 for counter */ + addi %r2, %r2, -8 /* pre dec for update on load */ + b im0 /* try second hash */ + +/* Create a faked ISI interrupt as the address was not found */ +do_isi_prot: + mfspr %r3, SPR_SRR1 /* get srr1 */ + andi. %r2, %r3, 0xffff /* clean upper srr1 */ + addis %r2, %r2, 0x0800 /* or in srr<4> = 1 to flag prot + * violation */ + b isi1 +do_isi: + mfspr %r3, SPR_SRR1 /* get srr1 */ + andi. %r2, %r3, 0xffff /* clean srr1 */ + addis %r2, %r2, 0x4000 /* or in srr1<1> = 1 to flag pte + * not found */ +isi1: + mtctr %r0 /* restore counter */ + mtspr SPR_SRR1, %r2 /* set srr1 */ + mfmsr %r0 /* get msr */ + xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ + mtcrf 0x80, %r3 /* restore CR0 */ + mtmsr %r0 /* flip back to the native gprs */ + ba EXC_ISI /* go to instr. access interrupt */ + +CNAME(imisssize) = .-CNAME(imisstrap) + +/* + * It's G2 specific. Data load TLB miss. + */ + .globl CNAME(dlmisstrap),CNAME(dlmisssize) +CNAME(dlmisstrap): + mfspr %r2, SPR_HASH1 /* get first pointer */ + addi %r1, 0, 8 /* load 8 for counter */ + mfctr %r0 /* save counter */ + mfspr %r3, SPR_DCMP /* get first compare value */ + addi %r2, %r2, -8 /* pre dec the pointer */ +dm0: + mtctr %r1 /* load counter */ +dm1: + lwzu %r1, 8(%r2) /* get next pte */ + cmp 0, 0, %r1, %r3 /* see if found pte */ + bdnzf 2, dm1 /* dec count br if cmp ne and if + * count not zero */ + bne data_sec_hash /* if not found set up second hash + * or exit */ + lwz %r1, +4(%r2) /* load tlb entry lower-word */ + mtctr %r0 /* restore counter */ + mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ + mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ + mtcrf 0x80, %r3 /* restore CR0 */ + mtspr SPR_RPA, %r1 /* set the pte */ + ori %r1, %r1, 0x100 /* set reference bit */ + srwi %r1, %r1, 8 /* get byte 7 of pte */ + tlbld %r0 /* load the dtlb */ + stb %r1, +6(%r2) /* update page table */ + rfi /* return to executing program */ + +data_sec_hash: + andi. %r1, %r3, 0x0040 /* see if we have done second hash */ + bne do_dsi /* if so, go to DSI interrupt */ + mfspr %r2, SPR_HASH2 /* get the second pointer */ + ori %r3, %r3, 0x0040 /* change the compare value */ + addi %r1, 0, 8 /* load 8 for counter */ + addi %r2, %r2, -8 /* pre dec for update on load */ + b dm0 /* try second hash */ + +CNAME(dlmisssize) = .-CNAME(dlmisstrap) + +/* + * It's G2 specific. Data store TLB miss. + */ + .globl CNAME(dsmisstrap),CNAME(dsmisssize) +CNAME(dsmisstrap): + mfspr %r2, SPR_HASH1 /* get first pointer */ + addi %r1, 0, 8 /* load 8 for counter */ + mfctr %r0 /* save counter */ + mfspr %r3, SPR_DCMP /* get first compare value */ + addi %r2, %r2, -8 /* pre dec the pointer */ +ds0: + mtctr %r1 /* load counter */ +ds1: + lwzu %r1, 8(%r2) /* get next pte */ + cmp 0, 0, %r1, %r3 /* see if found pte */ + bdnzf 2, ds1 /* dec count br if cmp ne and if + * count not zero */ + bne data_store_sec_hash /* if not found set up second hash + * or exit */ + lwz %r1, +4(%r2) /* load tlb entry lower-word */ + andi. %r3, %r1, 0x80 /* check the C-bit */ + beq data_store_chk_prot /* if (C==0) + * go check protection modes */ +ds2: + mtctr %r0 /* restore counter */ + mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ + mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ + mtcrf 0x80, %r3 /* restore CR0 */ + mtspr SPR_RPA, %r1 /* set the pte */ + tlbld %r0 /* load the dtlb */ + rfi /* return to executing program */ + +data_store_sec_hash: + andi. %r1, %r3, 0x0040 /* see if we have done second hash */ + bne do_dsi /* if so, go to DSI interrupt */ + mfspr %r2, SPR_HASH2 /* get the second pointer */ + ori %r3, %r3, 0x0040 /* change the compare value */ + addi %r1, 0, 8 /* load 8 for counter */ + addi %r2, %r2, -8 /* pre dec for update on load */ + b ds0 /* try second hash */ + +/* Check the protection before setting PTE(c-bit) */ +data_store_chk_prot: + rlwinm. %r3,%r1,30,0,1 /* test PP */ + bge- chk0 /* if (PP == 00 or PP == 01) + * goto chk0: */ + andi. %r3, %r1, 1 /* test PP[0] */ + beq+ chk2 /* return if PP[0] == 0 */ + b do_dsi_prot /* else DSIp */ +chk0: + mfspr %r3,SPR_SRR1 /* get old msr */ + andis. %r3,%r3,0x0008 /* test the KEY bit (SRR1-bit 12) */ + beq chk2 /* if (KEY==0) goto chk2: */ + b do_dsi_prot /* else do_dsi_prot */ +chk2: + ori %r1, %r1, 0x180 /* set reference and change bit */ + sth %r1, 6(%r2) /* update page table */ + b ds2 /* and back we go */ + +/* Create a faked DSI interrupt as the address was not found */ +do_dsi: + mfspr %r3, SPR_SRR1 /* get srr1 */ + rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for + * load/store, zero rest */ + addis %r1, %r1, 0x4000 /* or in dsisr<1> = 1 to flag pte + * not found */ + b dsi1 + +do_dsi_prot: + mfspr %r3, SPR_SRR1 /* get srr1 */ + rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for + *load/store, zero rest */ + addis %r1, %r1, 0x0800 /* or in dsisr<4> = 1 to flag prot + * violation */ + +dsi1: + mtctr %r0 /* restore counter */ + andi. %r2, %r3, 0xffff /* clear upper bits of srr1 */ + mtspr SPR_SRR1, %r2 /* set srr1 */ + mtspr SPR_DSISR, %r1 /* load the dsisr */ + mfspr %r1, SPR_DMISS /* get miss address */ + rlwinm. %r2,%r2,0,31,31 /* test LE bit */ + beq dsi2 /* if little endian then: */ + xor %r1, %r1, 0x07 /* de-mung the data address */ +dsi2: + mtspr SPR_DAR, %r1 /* put in dar */ + mfmsr %r0 /* get msr */ + xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ + mtcrf 0x80, %r3 /* restore CR0 */ + mtmsr %r0 /* flip back to the native gprs */ + ba EXC_DSI /* branch to DSI interrupt */ + +CNAME(dsmisssize) = .-CNAME(dsmisstrap) + + /* * Similar to the above for DSI * Has to handle BAT spills ==== //depot/projects/soc2008/vi0/efika/sys/powerpc/include/psl.h#2 (text+ko) ==== @@ -77,6 +77,7 @@ */ #define PSL_VEC 0x02000000 /* AltiVec vector unit available */ #define PSL_POW 0x00040000 /* power management */ +#define PSL_TGPR 0x00020000 /* temp. gpr remapping (mpc603e) */ #define PSL_ILE 0x00010000 /* interrupt endian mode (1 == le) */ #define PSL_EE 0x00008000 /* external interrupt enable */ #define PSL_PR 0x00004000 /* privilege mode (1 == user) */ @@ -86,6 +87,7 @@ #define PSL_SE 0x00000400 /* single-step trace enable */ #define PSL_BE 0x00000200 /* branch trace enable */ #define PSL_FE1 0x00000100 /* floating point interrupt mode 1 */ +#define PSL_CE 0x00000080 /* critical exception enable */ #define PSL_IP 0x00000040 /* interrupt prefix */ #define PSL_IR 0x00000020 /* instruction address relocation */ #define PSL_DR 0x00000010 /* data address relocation */
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