Date: Mon, 2 Jul 2012 21:11:01 +0000 (UTC) From: Marcel Moolenaar <marcel@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r238030 - head/sys/powerpc/booke Message-ID: <201207022111.q62LB1HK099753@svn.freebsd.org>
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Author: marcel Date: Mon Jul 2 21:11:01 2012 New Revision: 238030 URL: http://svn.freebsd.org/changeset/base/238030 Log: Implement cpu_flush_dcache(). This allows us to optimize __syncicache() for the common case in chich D-caches are coherent by virtue of busdma. Modified: head/sys/powerpc/booke/machdep.c Modified: head/sys/powerpc/booke/machdep.c ============================================================================== --- head/sys/powerpc/booke/machdep.c Mon Jul 2 21:01:03 2012 (r238029) +++ head/sys/powerpc/booke/machdep.c Mon Jul 2 21:11:01 2012 (r238030) @@ -473,7 +473,24 @@ cpu_pcpu_init(struct pcpu *pcpu, int cpu void cpu_flush_dcache(void *ptr, size_t len) { - /* TBD */ + register_t addr, off; + + /* + * Align the address to a cacheline and adjust the length + * accordingly. Then round the length to a multiple of the + * cacheline for easy looping. + */ + addr = (uintptr_t)ptr; + off = addr & (cacheline_size - 1); + addr -= off; + len = (len + off + cacheline_size - 1) & ~(cacheline_size - 1); + + while (len > 0) { + __asm __volatile ("dcbf 0,%0" :: "r"(addr)); + __asm __volatile ("sync"); + addr += cacheline_size; + len -= cacheline_size; + } } void
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