From owner-soc-status@freebsd.org Mon May 28 17:41:37 2018 Return-Path: Delivered-To: soc-status@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id C75F7F737F0 for ; Mon, 28 May 2018 17:41:37 +0000 (UTC) (envelope-from uddka@student.kit.edu) Received: from scc-mailout-kit-02.scc.kit.edu (scc-mailout-kit-02.scc.kit.edu [IPv6:2a00:1398:9:f712::810d:e752]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 6436A7901A; Mon, 28 May 2018 17:41:37 +0000 (UTC) (envelope-from uddka@student.kit.edu) Received: from tr-v1239-fse.scc.kit.edu ([2a00:1398:e:28::2] helo=server-01.fs-etec.kit.edu) by scc-mailout-kit-02.scc.kit.edu with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (envelope-from ) id 1fNM9F-0006ab-HM; Mon, 28 May 2018 19:41:35 +0200 Received: from Chris-TP (unknown [IPv6:2a00:1398:5:ee00:60d7:1374:864:93ee]) by server-01.fs-etec.kit.edu (Postfix) with ESMTPSA id 24908188EE0; Mon, 28 May 2018 19:41:33 +0200 (CEST) Date: Mon, 28 May 2018 19:40:54 +0200 From: Christian =?ISO-8859-1?Q?Kr=E4mer?= To: soc-status@freebsd.org Cc: Chuck Tuffli , Luiz Otavio O Souza Subject: User space interface for GPIO interrupts / Status Report Week 2 Message-Id: <20180528194054.b44df7621d933376ee686dde@student.kit.edu> X-Mailer: Sylpheed 3.7.0 (GTK+ 2.24.32; amd64-portbld-freebsd11.1) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: soc-status@freebsd.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Summer of Code Status Reports and Discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 May 2018 17:41:37 -0000 Dear all, since my last status report I implemented dynamic reconfiguration of the monitored pin and also started to write user space tools [1] to communicate with the gpiointr device driver [2]. Furthermore the gpiointr driver was moved away from simplebus, so that one instance of the gpiointr driver is now attached to each gpio controller. As a result no modified DTB file is needed any more and all GPIO pins can be configured in a consistent way like gpio(3) and gpioc. The configuration of, for example, pin 5 on gpiobus0 looks like this: $ gpiointr_config -f /dev/gpiointr0 5 Monitoring of the pin is still done by a read() syscall that will block until an interrupt on the pin is triggered. During this week I am going to implement locking mechanisms in order to avoid race conditions and start to move forward to dynamic resource management to be able to register interrupts for multiple pins on a specific gpiobus. Additionally the trigger type will become runtime configurable. Thanks, Chris [1] [2]