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Date: Sat, 24 May 2014 22:02:15 +0100
From: Andrew Turner <andrew@fubar.geek.nz>
To: Michael Tuexen <tuexen@freebsd.org>
Subject: Re: svn commit: r266083 - in head/sys/arm: arm include
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Cc: Hans Petter Selasky <hps@selasky.org>, svn-src-head@freebsd.org,
 svn-src-all@freebsd.org, src-committers@freebsd.org,
 Mark R V Murray <markm@FreeBSD.org>
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On Sat, 24 May 2014 21:09:56 +0200
Michael Tuexen <tuexen@freebsd.org> wrote:

> On 22 May 2014, at 09:09, Mark R V Murray <markm@FreeBSD.org> wrote:
> 
> > 
> > On 21 May 2014, at 21:15, Hans Petter Selasky <hps@selasky.org>
> > wrote:
> > 
> >> On 05/14/14 21:11, Mark Murray wrote:
> >>> Author: markm
> >>> Date: Wed May 14 19:11:15 2014
> >>> New Revision: 266083
> >>> URL: http://svnweb.freebsd.org/changeset/base/266083
> >>> 
> >>> Log:
> >>>  Give suitably-endowed ARMs a register similar to the x86 TSC
> >>> register.
> >>> 
> >> 
> >> Hi,
> >> 
> >> Regression issue:
> >> This commit prevents RPI-B from booting.
> > 
> > Thanks, I’ll look at it ASAP.
> Doesn't the ARM1176 use for example
> MRC p15, 0, <Rd>, c15, c12, 1    ; Read Cycle Counter Register
> to read the value, whereas the 
> you use 
> __asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=r" (ccnt));

On ARMv6 there is no guarantee of a cycle count register. On the
ARM1176 there is one in an implementation defined section of the system
control coprocessor. This is the c15 section above, and is accessible
as shown.

On ARMv7 there are optional performance monitor extensions. These are
in parts of the c9 section of the coprocessor. As it is optional there
is no requirement for implementers to include this functionality,
however I would expect the ARM designs to include it, and most non-ARM
designs are likely aiming for performance so will also include them.

If the ARMv7 processor has the performance extensions the existing code
appears correct to retrieve it.

Andrew