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Date:      Wed, 28 Nov 2012 18:05:24 +0200
From:      Konstantin Belousov <kostikbel@gmail.com>
To:        Andriy Gapon <avg@freebsd.org>
Cc:        "freebsd-emulation@freebsd.org" <freebsd-emulation@freebsd.org>, Alexander Motin <mav@freebsd.org>
Subject:   Re: VirtualBox 4.2.4 on FreeBSD 9.1-PRERELEASE problem: VMs behave very different when pinned to different cores
Message-ID:  <20121128160524.GT3013@kib.kiev.ua>
In-Reply-To: <50B62CB3.70101@FreeBSD.org>
References:  <CA%2Bkq2xvh3j5CM7UzRVfXCeLhHwpTY%2B_M7dCJx0c27NtV8EVJwg@mail.gmail.com> <CAE-m3X1UPsy%2Bwbqm_02JpXMr-UO3m7N6z_ZwY2HNo4GL0YUi1w@mail.gmail.com> <CA%2Bkq2xva61m_bHdzBZM2TYL5z7XiohvkxsYWtOyoBwQkpyvp0A@mail.gmail.com> <50AFAD05.1050604@FreeBSD.org> <CA%2Bkq2xv%2BU4ZnfK=1js4PRaNpTNdW-y-G50GV4%2BMVP0LugBf1pQ@mail.gmail.com> <50B25C17.20208@FreeBSD.org> <CA%2Bkq2xvjDa1BeuzPUuH99bgriEA-GJH36AZGiqScKSo4QZmHDg@mail.gmail.com> <50B62CB3.70101@FreeBSD.org>

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On Wed, Nov 28, 2012 at 05:24:35PM +0200, Andriy Gapon wrote:
> on 26/11/2012 09:10 Alex Chistyakov said the following:
> > CPU: Intel(R) Core(TM) i7-3930K CPU @ 3.20GHz (3200.18-MHz K8-class CPU)
> >   Origin =3D "GenuineIntel"  Id =3D 0x206d7  Family =3D 0x6  Model =3D =
0x2d
> > Stepping =3D 7
> > Features=3D0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,=
PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE>
> > Features2=3D0x1fbee3bf<SSE3,PCLMULQDQ,DTES64,MON,DS_CPL,VMX,EST,TM2,SSS=
E3,CX16,xTPR,PDCM,PCID,DCA,SSE4.1,SSE4.2,x2APIC,POPCNT,TSCDLT,AESNI,XSAVE,O=
SXSAVE,AVX>
> >   AMD Features=3D0x2c100800<SYSCALL,NX,Page1GB,RDTSCP,LM>
> >   AMD Features2=3D0x1<LAHF>
> >   TSC: P-state invariant, performance statistics
> >=20
>=20
> Is this a multi-socket system?
>=20
> It would be very strange that a modern CPU like this would have such a sk=
ew
> between TSC on different cores.
>=20
> On my Core i5-3570 I see that the _observed_ skew is no more than 100 tic=
ks (after
> many days of uptime).  It could be zero, in fact, given the inaccuracy of
> inter-core measurements.

I believe that Cores have single TSC per package, located in uncore.
And Core i7 cannot work in multi-socket systems.

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