From owner-freebsd-hackers Sun May 12 13:42:29 1996 Return-Path: owner-hackers Received: (from root@localhost) by freefall.freebsd.org (8.7.3/8.7.3) id NAA13453 for hackers-outgoing; Sun, 12 May 1996 13:42:29 -0700 (PDT) Received: from neon.Glock.COM (neon.glock.com [198.82.228.159]) by freefall.freebsd.org (8.7.3/8.7.3) with ESMTP id NAA13443 for ; Sun, 12 May 1996 13:42:25 -0700 (PDT) Received: (from mmead@localhost) by neon.Glock.COM (8.7.5/8.7.3) id QAA01594 for hackers@freebsd.org; Sun, 12 May 1996 16:42:23 -0400 (EDT) From: "matthew c. mead" Message-Id: <199605122042.QAA01594@neon.Glock.COM> Subject: Triton chipset with 256k cache caches 32M only? To: hackers@freebsd.org Date: Sun, 12 May 1996 16:42:23 -0400 (EDT) X-Mailer: ELM [version 2.4 PL24 ME8a] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: owner-hackers@freebsd.org X-Loop: FreeBSD.org Precedence: bulk I've got two machine with moderately fast CPUs in them. One is a Cyrix 6x86 120+ (@100Mhz), and the other is a P90 (clocked to 100Mhz). When I have 40M in the machines, the upper 8M is not cached, and my performance is roughly 2/3 of that when they just have 32M and all of the memory is cached. Does anyone know for sure whether or not 256K cache Triton chipsets only cache up to 32M? Anyone know what I can do to get the other 8M cached as well? I'd really like to have that extra 8M in there, but at 2/3 the performance, it aint gonna happen. Any help is greatly appreciated! -matt -- Matthew C. Mead mmead@Glock.COM http://www.Glock.COM/~mmead/