From owner-svn-src-all@FreeBSD.ORG Sat Feb 8 09:25:58 2014 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 49FA0498; Sat, 8 Feb 2014 09:25:58 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 270D219FB; Sat, 8 Feb 2014 09:25:58 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s189Pw6u001907; Sat, 8 Feb 2014 09:25:58 GMT (envelope-from dumbbell@svn.freebsd.org) Received: (from dumbbell@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s189PvjC001902; Sat, 8 Feb 2014 09:25:57 GMT (envelope-from dumbbell@svn.freebsd.org) Message-Id: <201402080925.s189PvjC001902@svn.freebsd.org> From: Jean-Sebastien Pedron Date: Sat, 8 Feb 2014 09:25:57 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-9@freebsd.org Subject: svn commit: r261625 - in stable/9/sys/dev/drm2: . i915 X-SVN-Group: stable-9 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 08 Feb 2014 09:25:58 -0000 Author: dumbbell Date: Sat Feb 8 09:25:56 2014 New Revision: 261625 URL: http://svnweb.freebsd.org/changeset/base/261625 Log: MFC r249041, r249249: drm and i915: Left-shift iic_msg.slave at creation time This is required because, in the radeon driver, we can't left-shift in a central place, like it was done in the i915 driver. Reviewed by: kib@, kan@, avg@ Tested by: kib@, avg@, Olivier Cochard-Labbé Modified: stable/9/sys/dev/drm2/drm_dp_iic_helper.c stable/9/sys/dev/drm2/drm_edid.c stable/9/sys/dev/drm2/i915/intel_iic.c stable/9/sys/dev/drm2/i915/intel_modes.c stable/9/sys/dev/drm2/i915/intel_sdvo.c Directory Properties: stable/9/sys/ (props changed) stable/9/sys/dev/ (props changed) Modified: stable/9/sys/dev/drm2/drm_dp_iic_helper.c ============================================================================== --- stable/9/sys/dev/drm2/drm_dp_iic_helper.c Sat Feb 8 08:50:44 2014 (r261624) +++ stable/9/sys/dev/drm2/drm_dp_iic_helper.c Sat Feb 8 09:25:56 2014 (r261625) @@ -146,7 +146,7 @@ iic_dp_aux_xfer(device_t idev, struct ii len = msgs[m].len; buf = msgs[m].buf; reading = (msgs[m].flags & IIC_M_RD) != 0; - ret = iic_dp_aux_address(idev, msgs[m].slave, reading); + ret = iic_dp_aux_address(idev, msgs[m].slave >> 1, reading); if (ret != 0) break; if (reading) { Modified: stable/9/sys/dev/drm2/drm_edid.c ============================================================================== --- stable/9/sys/dev/drm2/drm_edid.c Sat Feb 8 08:50:44 2014 (r261624) +++ stable/9/sys/dev/drm2/drm_edid.c Sat Feb 8 09:25:56 2014 (r261625) @@ -264,12 +264,12 @@ drm_do_probe_ddc_edid(device_t adapter, do { struct iic_msg msgs[] = { { - .slave = DDC_ADDR, + .slave = DDC_ADDR << 1, .flags = IIC_M_WR, .len = 1, .buf = &start, }, { - .slave = DDC_ADDR, + .slave = DDC_ADDR << 1, .flags = IIC_M_RD, .len = len, .buf = buf, Modified: stable/9/sys/dev/drm2/i915/intel_iic.c ============================================================================== --- stable/9/sys/dev/drm2/i915/intel_iic.c Sat Feb 8 08:50:44 2014 (r261624) +++ stable/9/sys/dev/drm2/i915/intel_iic.c Sat Feb 8 09:25:56 2014 (r261625) @@ -256,7 +256,7 @@ intel_gmbus_transfer(device_t idev, stru I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT | (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) | (len << GMBUS_BYTE_COUNT_SHIFT) | - (msgs[i].slave << GMBUS_SLAVE_ADDR_SHIFT) | + (msgs[i].slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); POSTING_READ(GMBUS2 + reg_offset); do { @@ -287,7 +287,7 @@ intel_gmbus_transfer(device_t idev, stru I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT | (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) | (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) | - (msgs[i].slave << GMBUS_SLAVE_ADDR_SHIFT) | + (msgs[i].slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); POSTING_READ(GMBUS2+reg_offset); @@ -397,17 +397,11 @@ intel_iic_quirk_xfer(device_t idev, stru IICBB_SETSCL(bridge_dev, 1); DELAY(I2C_RISEFALL_TIME); - /* convert slave addresses to format expected by iicbb */ - for (i = 0; i < nmsgs; i++) { - msgs[i].slave <<= 1; + for (i = 0; i < nmsgs - 1; i++) { /* force use of repeated start instead of default stop+start */ - if (i != (nmsgs - 1)) - msgs[i].flags |= IIC_M_NOSTOP; + msgs[i].flags |= IIC_M_NOSTOP; } ret = iicbus_transfer(idev, msgs, nmsgs); - /* restore the addresses */ - for (i = 0; i < nmsgs; i++) - msgs[i].slave >>= 1; IICBB_SETSDA(bridge_dev, 1); IICBB_SETSCL(bridge_dev, 1); intel_iic_quirk_set(dev_priv, false); Modified: stable/9/sys/dev/drm2/i915/intel_modes.c ============================================================================== --- stable/9/sys/dev/drm2/i915/intel_modes.c Sat Feb 8 08:50:44 2014 (r261624) +++ stable/9/sys/dev/drm2/i915/intel_modes.c Sat Feb 8 09:25:56 2014 (r261625) @@ -45,13 +45,13 @@ bool intel_ddc_probe(struct intel_encode u8 buf[2]; struct iic_msg msgs[] = { { - .slave = DDC_ADDR, + .slave = DDC_ADDR << 1, .flags = IIC_M_WR, .len = 1, .buf = out_buf, }, { - .slave = DDC_ADDR, + .slave = DDC_ADDR << 1, .flags = IIC_M_RD, .len = 1, .buf = buf, Modified: stable/9/sys/dev/drm2/i915/intel_sdvo.c ============================================================================== --- stable/9/sys/dev/drm2/i915/intel_sdvo.c Sat Feb 8 08:50:44 2014 (r261624) +++ stable/9/sys/dev/drm2/i915/intel_sdvo.c Sat Feb 8 09:25:56 2014 (r261625) @@ -266,13 +266,13 @@ static bool intel_sdvo_read_byte(struct { struct iic_msg msgs[] = { { - .slave = intel_sdvo->slave_addr, + .slave = intel_sdvo->slave_addr << 1, .flags = 0, .len = 1, .buf = &addr, }, { - .slave = intel_sdvo->slave_addr, + .slave = intel_sdvo->slave_addr << 1, .flags = IIC_M_RD, .len = 1, .buf = ch, @@ -454,14 +454,14 @@ intel_sdvo_write_cmd(struct intel_sdvo * intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); for (i = 0; i < args_len; i++) { - msgs[i].slave = intel_sdvo->slave_addr; + msgs[i].slave = intel_sdvo->slave_addr << 1; msgs[i].flags = 0; msgs[i].len = 2; msgs[i].buf = buf + 2 *i; buf[2*i + 0] = SDVO_I2C_ARG_0 - i; buf[2*i + 1] = ((const u8*)args)[i]; } - msgs[i].slave = intel_sdvo->slave_addr; + msgs[i].slave = intel_sdvo->slave_addr << 1; msgs[i].flags = 0; msgs[i].len = 2; msgs[i].buf = buf + 2*i; @@ -470,12 +470,12 @@ intel_sdvo_write_cmd(struct intel_sdvo * /* the following two are to read the response */ status = SDVO_I2C_CMD_STATUS; - msgs[i+1].slave = intel_sdvo->slave_addr; + msgs[i+1].slave = intel_sdvo->slave_addr << 1; msgs[i+1].flags = 0; msgs[i+1].len = 1; msgs[i+1].buf = &status; - msgs[i+2].slave = intel_sdvo->slave_addr; + msgs[i+2].slave = intel_sdvo->slave_addr << 1; msgs[i+2].flags = IIC_M_RD; msgs[i+2].len = 1; msgs[i+2].buf = &status;