From owner-svn-src-all@freebsd.org Wed May 4 15:49:05 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 02B08B2DDC1; Wed, 4 May 2016 15:49:05 +0000 (UTC) (envelope-from pfg@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 951431EE3; Wed, 4 May 2016 15:49:04 +0000 (UTC) (envelope-from pfg@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u44Fn37v029091; Wed, 4 May 2016 15:49:03 GMT (envelope-from pfg@FreeBSD.org) Received: (from pfg@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u44FmxAq029042; Wed, 4 May 2016 15:48:59 GMT (envelope-from pfg@FreeBSD.org) Message-Id: <201605041548.u44FmxAq029042@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: pfg set sender to pfg@FreeBSD.org using -f From: "Pedro F. Giffuni" Date: Wed, 4 May 2016 15:48:59 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r299069 - in head/sys/arm: amlogic/aml8726 arm at91 broadcom/bcm2835 cavium/cns11xx freescale/imx freescale/vybrid mv samsung/exynos ti ti/omap4 xilinx xscale/i8134x xscale/ixp425 xscal... X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 May 2016 15:49:05 -0000 Author: pfg Date: Wed May 4 15:48:59 2016 New Revision: 299069 URL: https://svnweb.freebsd.org/changeset/base/299069 Log: sys/arm: Minor spelling fixes. Only affects comments: no functional change. Modified: head/sys/arm/amlogic/aml8726/aml8726_mmc.c head/sys/arm/amlogic/aml8726/aml8726_mmc.h head/sys/arm/amlogic/aml8726/aml8726_sdxc-m8.c head/sys/arm/amlogic/aml8726/aml8726_sdxc-m8.h head/sys/arm/arm/cpufunc_asm_arm11.S head/sys/arm/arm/exception.S head/sys/arm/arm/gic.c head/sys/arm/arm/machdep.c head/sys/arm/arm/mpcore_timer.c head/sys/arm/arm/pmap-v4.c head/sys/arm/arm/pmap-v6.c head/sys/arm/arm/swtch-v4.S head/sys/arm/at91/at91_cfata.c head/sys/arm/at91/at91_machdep.c head/sys/arm/at91/at91_mci.c head/sys/arm/at91/at91_reset.S head/sys/arm/at91/at91reg.h head/sys/arm/at91/at91sam9260.c head/sys/arm/at91/if_ate.c head/sys/arm/at91/if_atereg.h head/sys/arm/broadcom/bcm2835/bcm2835_audio.c head/sys/arm/broadcom/bcm2835/bcm2835_dma.c head/sys/arm/cavium/cns11xx/if_ece.c head/sys/arm/freescale/imx/imx6_ipu.c head/sys/arm/freescale/imx/imx6_ssi.c head/sys/arm/freescale/vybrid/vf_uart.c head/sys/arm/mv/mpic.c head/sys/arm/mv/mv_common.c head/sys/arm/samsung/exynos/exynos5_usb_phy.c head/sys/arm/ti/omap4/omap4_prcm_clks.c head/sys/arm/ti/ti_i2c.c head/sys/arm/ti/ti_pinmux.c head/sys/arm/ti/ti_prcm.c head/sys/arm/ti/ti_scm.c head/sys/arm/ti/ti_sdma.c head/sys/arm/xilinx/zy7_slcr.c head/sys/arm/xscale/i8134x/crb_machdep.c head/sys/arm/xscale/i8134x/i81342reg.h head/sys/arm/xscale/ixp425/avila_machdep.c head/sys/arm/xscale/ixp425/cambria_gpio.c head/sys/arm/xscale/ixp425/ixp425_npe.c head/sys/arm/xscale/ixp425/ixp425_npereg.h head/sys/arm/xscale/ixp425/ixp425_qmgr.c head/sys/arm/xscale/pxa/pxa_machdep.c Modified: head/sys/arm/amlogic/aml8726/aml8726_mmc.c ============================================================================== --- head/sys/arm/amlogic/aml8726/aml8726_mmc.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/amlogic/aml8726/aml8726_mmc.c Wed May 4 15:48:59 2016 (r299069) @@ -240,7 +240,7 @@ aml8726_mmc_start_command(struct aml8726 * Start and transmission bits are per section 4.7.2 of the: * * SD Specifications Part 1 - * Physicaly Layer Simplified Specification + * Physical Layer Simplified Specification * Version 4.10 */ cmdr = AML_MMC_CMD_START_BIT | AML_MMC_CMD_TRANS_BIT_HOST | cmd->opcode; Modified: head/sys/arm/amlogic/aml8726/aml8726_mmc.h ============================================================================== --- head/sys/arm/amlogic/aml8726/aml8726_mmc.h Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/amlogic/aml8726/aml8726_mmc.h Wed May 4 15:48:59 2016 (r299069) @@ -39,7 +39,7 @@ * Read and write are per section 4.6.2 of the: * * SD Specifications Part 1 - * Physicaly Layer Simplified Specification + * Physical Layer Simplified Specification * Version 4.10 */ #define AML_MMC_CMD_TIMEOUT 50 Modified: head/sys/arm/amlogic/aml8726/aml8726_sdxc-m8.c ============================================================================== --- head/sys/arm/amlogic/aml8726/aml8726_sdxc-m8.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/amlogic/aml8726/aml8726_sdxc-m8.c Wed May 4 15:48:59 2016 (r299069) @@ -484,7 +484,7 @@ aml8726_sdxc_finish_command(struct aml87 if (stop_cmd != NULL) { /* - * If the original command executed successfuly, then + * If the original command executed successfully, then * the hardware will also have automatically executed * a stop command so don't bother with the one supplied * with the original request. Modified: head/sys/arm/amlogic/aml8726/aml8726_sdxc-m8.h ============================================================================== --- head/sys/arm/amlogic/aml8726/aml8726_sdxc-m8.h Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/amlogic/aml8726/aml8726_sdxc-m8.h Wed May 4 15:48:59 2016 (r299069) @@ -38,7 +38,7 @@ * Read and write are per section 4.6.2 of the: * * SD Specifications Part 1 - * Physicaly Layer Simplified Specification + * Physical Layer Simplified Specification * Version 4.10 */ #define AML_SDXC_CMD_TIMEOUT 50 Modified: head/sys/arm/arm/cpufunc_asm_arm11.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_arm11.S Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/arm/cpufunc_asm_arm11.S Wed May 4 15:48:59 2016 (r299069) @@ -30,7 +30,7 @@ * * ARM11 assembly functions for CPU / MMU / TLB specific operations * - * XXX We make no attempt at present to take advantage of the v6 memroy + * XXX We make no attempt at present to take advantage of the v6 memory * architecture or physically tagged cache. */ Modified: head/sys/arm/arm/exception.S ============================================================================== --- head/sys/arm/arm/exception.S Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/arm/exception.S Wed May 4 15:48:59 2016 (r299069) @@ -175,7 +175,7 @@ _C_LABEL(dtrace_invop_jump_addr): ldr r4, [r5, #4]; /* reset it to point at the */ \ cmp r4, #0xffffffff; /* end of memory if necessary; */ \ movne r1, #0xffffffff; /* leave value in r4 for later */ \ - strne r1, [r5, #4]; /* comparision against PC. */ \ + strne r1, [r5, #4]; /* comparison against PC. */ \ ldr r3, [r5]; /* Retrieve global RAS_START */ \ cmp r3, #0; /* and reset it if non-zero. */ \ movne r1, #0; /* If non-zero RAS_START and */ \ Modified: head/sys/arm/arm/gic.c ============================================================================== --- head/sys/arm/arm/gic.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/arm/gic.c Wed May 4 15:48:59 2016 (r299069) @@ -1231,7 +1231,7 @@ arm_gic_next_irq(struct arm_gic_softc *s active_irq = gic_c_read_4(sc, GICC_IAR); /* - * Immediatly EOIR the SGIs, because doing so requires the other + * Immediately EOIR the SGIs, because doing so requires the other * bits (ie CPU number), not just the IRQ number, and we do not * have this information later. */ Modified: head/sys/arm/arm/machdep.c ============================================================================== --- head/sys/arm/arm/machdep.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/arm/machdep.c Wed May 4 15:48:59 2016 (r299069) @@ -36,7 +36,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * Machine dependant functions for kernel setup + * Machine dependent functions for kernel setup * * Created : 17/09/94 * Updated : 18/04/01 updated for new wscons Modified: head/sys/arm/arm/mpcore_timer.c ============================================================================== --- head/sys/arm/arm/mpcore_timer.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/arm/mpcore_timer.c Wed May 4 15:48:59 2016 (r299069) @@ -367,7 +367,7 @@ attach_et(struct arm_tmr_softc *sc) * globally and registers both the timecount and eventtimer objects. * * RETURNS - * Zero on sucess or ENXIO if an error occuried. + * Zero on success or ENXIO if an error occuried. */ static int arm_tmr_attach(device_t dev) @@ -457,7 +457,7 @@ EARLY_DRIVER_MODULE(mp_tmr, ofwbus, arm_ /* * Handle a change in clock frequency. The mpcore timer runs at half the CPU * frequency. When the CPU frequency changes due to power-saving or thermal - * managment, the platform-specific code that causes the frequency change calls + * management, the platform-specific code that causes the frequency change calls * this routine to inform the clock driver, and we in turn inform the event * timer system, which actually updates the value in et->frequency for us and * reschedules the current event(s) in a way that's atomic with respect to Modified: head/sys/arm/arm/pmap-v4.c ============================================================================== --- head/sys/arm/arm/pmap-v4.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/arm/pmap-v4.c Wed May 4 15:48:59 2016 (r299069) @@ -126,7 +126,7 @@ * * pmap.c * - * Machine dependant vm stuff + * Machine dependent vm stuff * * Created : 20/09/94 */ @@ -1386,9 +1386,9 @@ pmap_clearbit(struct vm_page *pg, u_int * * Don't turn caching on again if this is a * modified emulation. This would be - * inconsitent with the settings created by + * inconsistent with the settings created by * pmap_fix_cache(). Otherwise, it's safe - * to re-enable cacheing. + * to re-enable caching. * * There's no need to call pmap_fix_cache() * here: all pages are losing their write Modified: head/sys/arm/arm/pmap-v6.c ============================================================================== --- head/sys/arm/arm/pmap-v6.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/arm/pmap-v6.c Wed May 4 15:48:59 2016 (r299069) @@ -705,7 +705,7 @@ pmap_preboot_get_pages(u_int num) } /* - * The fundamental initalization of PMAP stuff. + * The fundamental initialization of PMAP stuff. * * Some things already happened in locore.S and some things could happen * before pmap_bootstrap_prepare() is called, so let's recall what is done: @@ -1210,7 +1210,7 @@ pmap_bootstrap(vm_offset_t firstaddr) /* * Note that in very short time in initarm(), we are going to - * initialize phys_avail[] array and no futher page allocation + * initialize phys_avail[] array and no further page allocation * can happen after that until vm subsystem will be initialized. */ kernel_vm_end_new = kernel_vm_end; Modified: head/sys/arm/arm/swtch-v4.S ============================================================================== --- head/sys/arm/arm/swtch-v4.S Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/arm/swtch-v4.S Wed May 4 15:48:59 2016 (r299069) @@ -296,7 +296,7 @@ ENTRY(cpu_switch) beq .Lcs_context_switched /* yes! */ /* - * Definately need to flush the cache. + * Definitely need to flush the cache. */ ldr r1, .Lcpufuncs Modified: head/sys/arm/at91/at91_cfata.c ============================================================================== --- head/sys/arm/at91/at91_cfata.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/at91/at91_cfata.c Wed May 4 15:48:59 2016 (r299069) @@ -26,7 +26,7 @@ * common memory mode. Interrupts are driven by polling. The driver * implements an ATA bridge and attached ATA channel driver on top * of it. - * NOTE WELL: this driver uses polling mode. To achive an acceptable + * NOTE WELL: this driver uses polling mode. To achieve an acceptable * operating speed you will probably want to use HZ=2000 in kernel * config. */ Modified: head/sys/arm/at91/at91_machdep.c ============================================================================== --- head/sys/arm/at91/at91_machdep.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/at91/at91_machdep.c Wed May 4 15:48:59 2016 (r299069) @@ -36,7 +36,7 @@ * * machdep.c * - * Machine dependant functions for kernel setup + * Machine dependent functions for kernel setup * * This file needs a lot of work. * Modified: head/sys/arm/at91/at91_mci.c ============================================================================== --- head/sys/arm/at91/at91_mci.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/at91/at91_mci.c Wed May 4 15:48:59 2016 (r299069) @@ -92,7 +92,7 @@ __FBSDID("$FreeBSD$"); * speed is 25MHz and the next highest speed is 15MHz or less. This appears * to work on virtually all SD cards, since it is what this driver has been * doing prior to the introduction of this option, where the overclocking vs - * underclocking decision was automaticly "overclock". Modern SD cards can + * underclocking decision was automatically "overclock". Modern SD cards can * run at 45mhz/1-bit in standard mode (high speed mode enable commands not * sent) without problems. * @@ -212,7 +212,7 @@ at91_bswap_buf(struct at91_mci_softc *sc /* * If the hardware doesn't need byte-swapping, let bcopy() do the * work. Use bounce buffer even if we don't need byteswap, since - * buffer may straddle a page boundry, and we don't handle + * buffer may straddle a page boundary, and we don't handle * multi-segment transfers in hardware. Seen from 'bsdlabel -w' which * uses raw geom access to the volume. Greg Ansley (gja (at) * ansley.com) Modified: head/sys/arm/at91/at91_reset.S ============================================================================== --- head/sys/arm/at91/at91_reset.S Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/at91/at91_reset.S Wed May 4 15:48:59 2016 (r299069) @@ -14,7 +14,7 @@ __FBSDID("$FreeBSD$"); /* * From AT91SAM9G20 Datasheet errata 44:3.5: * - * When User Reset occurs durring SDRAM read acces, eh SDRAM clock is turned + * When User Reset occurs during SDRAM read access, the SDRAM clock is turned * off while data are ready to be read on the data bus. The SDRAM maintains * the data until the clock restarts. * Modified: head/sys/arm/at91/at91reg.h ============================================================================== --- head/sys/arm/at91/at91reg.h Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/at91/at91reg.h Wed May 4 15:48:59 2016 (r299069) @@ -39,9 +39,9 @@ #define AT91_PA_BASE 0xf0000000 /* A few things that we count on being the same - * throught the whole family of SOCs */ + * throughout the whole family of SOCs */ -/* SYSC System Controler */ +/* SYSC System Controller */ /* System Registers */ #define AT91_SYS_BASE 0xffff000 #define AT91_SYS_SIZE 0x1000 Modified: head/sys/arm/at91/at91sam9260.c ============================================================================== --- head/sys/arm/at91/at91sam9260.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/at91/at91sam9260.c Wed May 4 15:48:59 2016 (r299069) @@ -188,7 +188,7 @@ at91_clock_init(void) * PMC alogrithm choose the divisor that causes the input clock * to be near the optimal 2 MHz per datasheet. We know * we are going to be using this for the USB clock at 96 MHz. - * Causes no extra frequency deviation for all recomended crystal + * Causes no extra frequency deviation for all recommended crystal * values. See Note 1, table 40-16 SAM9260 doc. */ clk = at91_pmc_clock_ref("pllb"); Modified: head/sys/arm/at91/if_ate.c ============================================================================== --- head/sys/arm/at91/if_ate.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/at91/if_ate.c Wed May 4 15:48:59 2016 (r299069) @@ -651,7 +651,7 @@ ate_activate(device_t dev) ate_getaddr, &sc->tx_desc_phys, 0) != 0) goto errout; - /* Initilize descriptors; mark all empty */ + /* Initialize descriptors; mark all empty */ for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { sc->tx_descs[i].addr =0; sc->tx_descs[i].status = ETHB_TX_USED; @@ -919,7 +919,7 @@ ate_intr(void *xsc) /* * Simulate SAM9 FIRST/LAST bits for RM9200. * RM9200 EMAC has only on Rx buffer per packet. - * But sometime we are handed a zero lenght packet. + * But sometime we are handed a zero length packet. */ if ((rxdhead->status & ETH_LEN_MASK) == 0) rxdhead->status = 0; /* Mark error */ @@ -980,7 +980,7 @@ ate_intr(void *xsc) do { /* Last buffer may just be 1-4 bytes of FCS so remain - * may be zero for last decriptor. */ + * may be zero for last descriptor. */ if (remain > 0) { /* Make sure we get the current bytes */ bus_dmamap_sync(sc->rx_tag, sc->rx_map[sc->rxhead], @@ -989,7 +989,7 @@ ate_intr(void *xsc) count = MIN(remain, sc->rx_buf_size); /* XXX Performance robbing copy. Could - * recieve directly to mbufs if not an + * receive directly to mbufs if not an * RM9200. And even then we could likely * copy just the protocol headers. XXX */ m_append(mb, count, sc->rx_buf[sc->rxhead]); @@ -1468,7 +1468,7 @@ ate_miibus_readreg(device_t dev, int phy int val; /* - * XXX if we implement agressive power savings, then we need + * XXX if we implement aggressive power savings, then we need * XXX to make sure that the clock to the emac is on here */ @@ -1488,7 +1488,7 @@ ate_miibus_writereg(device_t dev, int ph struct ate_softc *sc; /* - * XXX if we implement agressive power savings, then we need + * XXX if we implement aggressive power savings, then we need * XXX to make sure that the clock to the emac is on here */ Modified: head/sys/arm/at91/if_atereg.h ============================================================================== --- head/sys/arm/at91/if_atereg.h Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/at91/if_atereg.h Wed May 4 15:48:59 2016 (r299069) @@ -28,7 +28,7 @@ #ifndef ARM_AT91_IF_ATEREG_H #define ARM_AT91_IF_ATEREG_H -/* deines begining ETHB_ are EMACB (newer SAM9 hardware) versions only */ +/* Defines beginning ETHB_ are EMACB (newer SAM9 hardware) versions only. */ #define ETH_CTL 0x00 /* EMAC Control Register */ #define ETH_CFG 0x04 /* EMAC Configuration Register */ @@ -191,7 +191,7 @@ typedef struct { #define ETH_MAC_LOCAL_3 (1U << 24) /* Packet matched addr 3 */ #define ETH_MAC_LOCAL_2 (1U << 25) /* Packet matched addr 2 */ #define ETH_MAC_LOCAL_1 (1U << 26) /* Packet matched addr 1 */ -#define ETH_MAC_UNK (1U << 27) /* Unkown source address RFU */ +#define ETH_MAC_UNK (1U << 27) /* Unknown source address RFU */ #define ETH_MAC_EXT (1U << 28) /* External Address */ #define ETH_MAC_UCAST (1U << 29) /* Unicast hash match */ #define ETH_MAC_MCAST (1U << 30) /* Multicast hash match */ Modified: head/sys/arm/broadcom/bcm2835/bcm2835_audio.c ============================================================================== --- head/sys/arm/broadcom/bcm2835/bcm2835_audio.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/broadcom/bcm2835/bcm2835_audio.c Wed May 4 15:48:59 2016 (r299069) @@ -828,7 +828,7 @@ bcm2835_audio_attach(device_t dev) /* * We need interrupts enabled for VCHI to work properly, - * so delay intialization until it happens + * so delay initialization until it happens. */ sc->intr_hook.ich_func = bcm2835_audio_delayed_init; sc->intr_hook.ich_arg = sc; Modified: head/sys/arm/broadcom/bcm2835/bcm2835_dma.c ============================================================================== --- head/sys/arm/broadcom/bcm2835/bcm2835_dma.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/broadcom/bcm2835/bcm2835_dma.c Wed May 4 15:48:59 2016 (r299069) @@ -278,7 +278,7 @@ bcm_dma_init(device_t dev) /* * Least alignment for busdma-allocated stuff is cache - * line size, so just make sure nothing stupid happend + * line size, so just make sure nothing stupid happened * and we got properly aligned address */ if ((uintptr_t)cb_virt & 0x1f) { @@ -539,7 +539,7 @@ bcm_dma_reg_dump(int ch) * ch - channel number * src, dst - source and destination address in * ARM physical memory address space. - * len - amount of bytes to be transfered + * len - amount of bytes to be transferred * * Returns 0 on success, -1 otherwise */ Modified: head/sys/arm/cavium/cns11xx/if_ece.c ============================================================================== --- head/sys/arm/cavium/cns11xx/if_ece.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/cavium/cns11xx/if_ece.c Wed May 4 15:48:59 2016 (r299069) @@ -1685,7 +1685,7 @@ ece_encap(struct ece_softc *sc, struct m /* * After all descriptors are set, we set the flags to start the - * sending proces. + * sending process. */ for (seg = 0; seg < nsegs; seg++) { desc->cown = 0; Modified: head/sys/arm/freescale/imx/imx6_ipu.c ============================================================================== --- head/sys/arm/freescale/imx/imx6_ipu.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/freescale/imx/imx6_ipu.c Wed May 4 15:48:59 2016 (r299069) @@ -872,7 +872,7 @@ ipu_init_buffer(struct ipu_softc *sc) stride = sc->sc_mode->hdisplay * MODE_BPP / 8; - /* init channel paramters */ + /* init channel parameters */ CH_PARAM_RESET(¶m); /* XXX: interlaced modes are not supported yet */ CH_PARAM_SET_FW(¶m, sc->sc_mode->hdisplay - 1); Modified: head/sys/arm/freescale/imx/imx6_ssi.c ============================================================================== --- head/sys/arm/freescale/imx/imx6_ssi.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/freescale/imx/imx6_ssi.c Wed May 4 15:48:59 2016 (r299069) @@ -738,7 +738,7 @@ ssi_attach(device_t dev) sc->lock = snd_mtxcreate(device_get_nameunit(dev), "ssi softc"); if (sc->lock == NULL) { - device_printf(dev, "Cant create mtx\n"); + device_printf(dev, "Can't create mtx\n"); return (ENXIO); } @@ -764,7 +764,7 @@ ssi_attach(device_t dev) /* * Maximum possible DMA buffer. - * Will be used partialy to match 24 bit word. + * Will be used partially to match 24 bit word. */ sc->dma_size = 131072; Modified: head/sys/arm/freescale/vybrid/vf_uart.c ============================================================================== --- head/sys/arm/freescale/vybrid/vf_uart.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/freescale/vybrid/vf_uart.c Wed May 4 15:48:59 2016 (r299069) @@ -205,7 +205,7 @@ uart_reinit(struct uart_softc *sc, int c bas = &sc->sc_bas; if (!bas) { - printf("Error: cant reconfigure bas\n"); + printf("Error: can't reconfigure bas\n"); return; } Modified: head/sys/arm/mv/mpic.c ============================================================================== --- head/sys/arm/mv/mpic.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/mv/mpic.c Wed May 4 15:48:59 2016 (r299069) @@ -564,7 +564,7 @@ mv_msi_data(int irq, uint64_t *addr, uin node = ofw_bus_get_node(mv_mpic_sc->sc_dev); - /* Get physical addres of register space */ + /* Get physical address of register space */ error = fdt_get_range(OF_parent(node), 0, &phys, &size); if (error) { printf("%s: Cannot get register physical address, err:%d", Modified: head/sys/arm/mv/mv_common.c ============================================================================== --- head/sys/arm/mv/mv_common.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/mv/mv_common.c Wed May 4 15:48:59 2016 (r299069) @@ -1398,7 +1398,7 @@ decode_win_pcie_setup(u_long base) /* * Upper 16 bits in BAR register is interpreted as BAR size - * (in 64 kB units) plus 64kB, so substract 0x10000 + * (in 64 kB units) plus 64kB, so subtract 0x10000 * form value passed to register to get correct value. */ size -= 0x10000; Modified: head/sys/arm/samsung/exynos/exynos5_usb_phy.c ============================================================================== --- head/sys/arm/samsung/exynos/exynos5_usb_phy.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/samsung/exynos/exynos5_usb_phy.c Wed May 4 15:48:59 2016 (r299069) @@ -161,7 +161,7 @@ vbus_on(struct usb_phy_softc *sc) gpio_dev = devclass_get_device(devclass_find("gpio"), 0); if (gpio_dev == NULL) { - device_printf(sc->dev, "cant find gpio_dev\n"); + device_printf(sc->dev, "can't find gpio_dev\n"); return (1); } Modified: head/sys/arm/ti/omap4/omap4_prcm_clks.c ============================================================================== --- head/sys/arm/ti/omap4/omap4_prcm_clks.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/ti/omap4/omap4_prcm_clks.c Wed May 4 15:48:59 2016 (r299069) @@ -1329,7 +1329,7 @@ omap4_clk_hsusbhost_accessible(struct ti * Inherits the locks from the omap_prcm driver, no internal locking. * * RETURNS: - * Returns 0 if sucessful otherwise a negative error code on failure. + * Returns 0 if successful otherwise a negative error code on failure. */ static int omap4_clk_hsusbhost_set_source(struct ti_clock_dev *clkdev, Modified: head/sys/arm/ti/ti_i2c.c ============================================================================== --- head/sys/arm/ti/ti_i2c.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/ti/ti_i2c.c Wed May 4 15:48:59 2016 (r299069) @@ -236,7 +236,7 @@ ti_i2c_transfer_intr(struct ti_i2c_softc if (status & I2C_STAT_RDR) { /* * Receive draining interrupt - last data received. - * The set FIFO threshold wont be reached to trigger + * The set FIFO threshold won't be reached to trigger * RRDY. */ ti_i2c_dbg(sc, "Receive draining interrupt\n"); @@ -272,7 +272,7 @@ ti_i2c_transfer_intr(struct ti_i2c_softc /* * Transmit draining interrupt - FIFO level is below * the set threshold and the amount of data still to - * be transferred wont reach the set FIFO threshold. + * be transferred won't reach the set FIFO threshold. */ ti_i2c_dbg(sc, "Transmit draining interrupt\n"); Modified: head/sys/arm/ti/ti_pinmux.c ============================================================================== --- head/sys/arm/ti/ti_pinmux.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/ti/ti_pinmux.c Wed May 4 15:48:59 2016 (r299069) @@ -394,7 +394,7 @@ ti_pinmux_probe(device_t dev) * @dev: new device * * RETURNS - * Zero on sucess or ENXIO if an error occuried. + * Zero on success or ENXIO if an error occuried. */ static int ti_pinmux_attach(device_t dev) Modified: head/sys/arm/ti/ti_prcm.c ============================================================================== --- head/sys/arm/ti/ti_prcm.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/ti/ti_prcm.c Wed May 4 15:48:59 2016 (r299069) @@ -31,7 +31,7 @@ */ /** - * Power, Reset and Clock Managment Module + * Power, Reset and Clock Management Module * * This is a very simple driver wrapper around the PRCM set of registers in * the OMAP3 chip. It allows you to turn on and off things like the functional Modified: head/sys/arm/ti/ti_scm.c ============================================================================== --- head/sys/arm/ti/ti_scm.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/ti/ti_scm.c Wed May 4 15:48:59 2016 (r299069) @@ -111,7 +111,7 @@ ti_scm_probe(device_t dev) * globally and registers both the timecount and eventtimer objects. * * RETURNS - * Zero on sucess or ENXIO if an error occuried. + * Zero on success or ENXIO if an error occuried. */ static int ti_scm_attach(device_t dev) Modified: head/sys/arm/ti/ti_sdma.c ============================================================================== --- head/sys/arm/ti/ti_sdma.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/ti/ti_sdma.c Wed May 4 15:48:59 2016 (r299069) @@ -446,7 +446,7 @@ ti_sdma_deactivate_channel(unsigned int * ti_sdma_disable_channel_irq - disables IRQ's on the given channel * @ch: the channel to disable IRQ's on * - * Disable interupt generation for the given channel. + * Disable interrupt generation for the given channel. * * LOCKING: * DMA registers protected by internal mutex @@ -608,7 +608,7 @@ ti_sdma_get_channel_status(unsigned int /** * ti_sdma_start_xfer - starts a DMA transfer - * @ch: the channel number to set the endianess of + * @ch: the channel number to set the endianness of * @src_paddr: the source phsyical address * @dst_paddr: the destination phsyical address * @frmcnt: the number of frames per block @@ -707,7 +707,7 @@ ti_sdma_start_xfer(unsigned int ch, unsi * frmcnt = 1, elmcnt = 512, pktsize = 128 * * Total transfer bytes = 1 * 512 = 512 elements or 2048 bytes - * Packets transfered = 128 / 512 = 4 + * Packets transferred = 128 / 512 = 4 * * * LOCKING: @@ -787,7 +787,7 @@ ti_sdma_start_xfer_packet(unsigned int c /** * ti_sdma_stop_xfer - stops any currently active transfers - * @ch: the channel number to set the endianess of + * @ch: the channel number to set the endianness of * * This function call is effectively a NOP if no transaction is in progress. * @@ -835,10 +835,10 @@ ti_sdma_stop_xfer(unsigned int ch) } /** - * ti_sdma_set_xfer_endianess - sets the endianess of subsequent transfers - * @ch: the channel number to set the endianess of - * @src: the source endianess (either DMA_ENDIAN_LITTLE or DMA_ENDIAN_BIG) - * @dst: the destination endianess (either DMA_ENDIAN_LITTLE or DMA_ENDIAN_BIG) + * ti_sdma_set_xfer_endianess - sets the endianness of subsequent transfers + * @ch: the channel number to set the endianness of + * @src: the source endianness (either DMA_ENDIAN_LITTLE or DMA_ENDIAN_BIG) + * @dst: the destination endianness (either DMA_ENDIAN_LITTLE or DMA_ENDIAN_BIG) * * * LOCKING: @@ -879,9 +879,9 @@ ti_sdma_set_xfer_endianess(unsigned int /** * ti_sdma_set_xfer_burst - sets the source and destination element size * @ch: the channel number to set the burst settings of - * @src: the source endianess (either DMA_BURST_NONE, DMA_BURST_16, DMA_BURST_32 + * @src: the source endianness (either DMA_BURST_NONE, DMA_BURST_16, DMA_BURST_32 * or DMA_BURST_64) - * @dst: the destination endianess (either DMA_BURST_NONE, DMA_BURST_16, + * @dst: the destination endianness (either DMA_BURST_NONE, DMA_BURST_16, * DMA_BURST_32 or DMA_BURST_64) * * This function sets the size of the elements for all subsequent transfers. @@ -923,7 +923,7 @@ ti_sdma_set_xfer_burst(unsigned int ch, /** * ti_sdma_set_xfer_data_type - driver attach function - * @ch: the channel number to set the endianess of + * @ch: the channel number to set the endianness of * @type: the xfer data type (either DMA_DATA_8BITS_SCALAR, DMA_DATA_16BITS_SCALAR * or DMA_DATA_32BITS_SCALAR) * @@ -1065,7 +1065,7 @@ ti_sdma_sync_params(unsigned int ch, uns /** * ti_sdma_set_addr_mode - driver attach function - * @ch: the channel number to set the endianess of + * @ch: the channel number to set the endianness of * @rd_mode: the xfer source addressing mode (either DMA_ADDR_CONSTANT, * DMA_ADDR_POST_INCREMENT, DMA_ADDR_SINGLE_INDEX or * DMA_ADDR_DOUBLE_INDEX) Modified: head/sys/arm/xilinx/zy7_slcr.c ============================================================================== --- head/sys/arm/xilinx/zy7_slcr.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/xilinx/zy7_slcr.c Wed May 4 15:48:59 2016 (r299069) @@ -177,7 +177,7 @@ zy7_slcr_preload_pl(void) /* After PL configuration, enable level shifters and deassert top-level * PL resets. Called from zy7_devcfg.c. Optionally, the level shifters * can be left disabled but that's rare of an FPGA application. That option - * is controled by a sysctl in the devcfg driver. + * is controlled by a sysctl in the devcfg driver. */ void zy7_slcr_postload_pl(int en_level_shifters) Modified: head/sys/arm/xscale/i8134x/crb_machdep.c ============================================================================== --- head/sys/arm/xscale/i8134x/crb_machdep.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/xscale/i8134x/crb_machdep.c Wed May 4 15:48:59 2016 (r299069) @@ -38,7 +38,7 @@ * * machdep.c * - * Machine dependant functions for kernel setup + * Machine dependent functions for kernel setup * * This file needs a lot of work. * Modified: head/sys/arm/xscale/i8134x/i81342reg.h ============================================================================== --- head/sys/arm/xscale/i8134x/i81342reg.h Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/xscale/i8134x/i81342reg.h Wed May 4 15:48:59 2016 (r299069) @@ -184,7 +184,7 @@ #define ATU_IATVR2 0x005c /* Inbound ATU Translate Value Register 2 */ #define ATU_IAUTVR2 0x0060 /* Inbound ATU Upper Translate Value Register 2*/ #define ATU_ERLR 0x0064 /* Expansion ROM Limit Register */ -#define ATU_ERTVR 0x0068 /* Expansion ROM Translater Value Register */ +#define ATU_ERTVR 0x0068 /* Expansion ROM Translator Value Register */ #define ATU_ERUTVR 0x006c /* Expansion ROM Upper Translate Value Register*/ #define ATU_CR 0x0070 /* ATU Configuration Register */ #define ATU_CR_OUT_EN (1 << 1) Modified: head/sys/arm/xscale/ixp425/avila_machdep.c ============================================================================== --- head/sys/arm/xscale/ixp425/avila_machdep.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/xscale/ixp425/avila_machdep.c Wed May 4 15:48:59 2016 (r299069) @@ -38,7 +38,7 @@ * * machdep.c * - * Machine dependant functions for kernel setup + * Machine dependent functions for kernel setup * * This file needs a lot of work. * Modified: head/sys/arm/xscale/ixp425/cambria_gpio.c ============================================================================== --- head/sys/arm/xscale/ixp425/cambria_gpio.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/xscale/ixp425/cambria_gpio.c Wed May 4 15:48:59 2016 (r299069) @@ -32,7 +32,7 @@ * The Cambria PLD does not set the i2c ack bit after each write, if we used the * regular iicbus interface it would abort the xfer after the address byte * times out and not write our latch. To get around this we grab the iicbus and - * then do our own bit banging. This is a comprimise to changing all the iicbb + * then do our own bit banging. This is a compromise to changing all the iicbb * device methods to allow a flag to be passed down and is similir to how Linux * does it. * Modified: head/sys/arm/xscale/ixp425/ixp425_npe.c ============================================================================== --- head/sys/arm/xscale/ixp425/ixp425_npe.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/xscale/ixp425/ixp425_npe.c Wed May 4 15:48:59 2016 (r299069) @@ -507,7 +507,7 @@ ixpnpe_load_firmware(struct ixpnpe_softc /* * If download was successful, store image Id in list of - * currently loaded images. If a critical error occured + * currently loaded images. If a critical error occurred * during download, record that the NPE has an invalid image */ mtx_lock(&sc->sc_mtx); @@ -864,7 +864,7 @@ npe_cpu_reset(struct ixpnpe_softc *sc) while (npe_checkbits(sc, IX_NPEDL_REG_OFFSET_STAT, IX_NPEDL_MASK_STAT_IFNE)) { /* - * Step execution of the NPE intruction to read inFIFO using + * Step execution of the NPE instruction to read inFIFO using * the Debug Executing Context stack. */ error = npe_cpu_step(sc, IX_NPEDL_INSTR_RD_FIFO, 0, 0); @@ -1307,7 +1307,7 @@ npe_logical_reg_write(struct ixpnpe_soft ((regVal & IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA) << IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA); - /* step execution of NPE intruction using Debug ECS */ + /* step execution of NPE instruction using Debug ECS */ error = npe_cpu_step(sc, npeInstruction, ctxtNum, IX_NPEDL_WR_INSTR_LDUR); } Modified: head/sys/arm/xscale/ixp425/ixp425_npereg.h ============================================================================== --- head/sys/arm/xscale/ixp425/ixp425_npereg.h Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/xscale/ixp425/ixp425_npereg.h Wed May 4 15:48:59 2016 (r299069) @@ -125,7 +125,7 @@ /* * Reset value for Mailbox (MBST) register - * NOTE that if used, it should be complemented with an NPE intruction + * NOTE that if used, it should be complemented with an NPE instruction * to clear the Mailbox at the NPE side as well */ #define IX_NPEDL_REG_RESET_MBST 0x0000F0F0 Modified: head/sys/arm/xscale/ixp425/ixp425_qmgr.c ============================================================================== --- head/sys/arm/xscale/ixp425/ixp425_qmgr.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/xscale/ixp425/ixp425_qmgr.c Wed May 4 15:48:59 2016 (r299069) @@ -421,7 +421,7 @@ ixpqmgr_qwrite(int qId, uint32_t entry) return ENOSPC; } /* - * No overflow occured : someone is draining the queue + * No overflow occurred : someone is draining the queue * and the current counter needs to be * updated from the current number of entries in the queue */ Modified: head/sys/arm/xscale/pxa/pxa_machdep.c ============================================================================== --- head/sys/arm/xscale/pxa/pxa_machdep.c Wed May 4 15:27:09 2016 (r299068) +++ head/sys/arm/xscale/pxa/pxa_machdep.c Wed May 4 15:48:59 2016 (r299069) @@ -38,7 +38,7 @@ * * machdep.c * - * Machine dependant functions for kernel setup + * Machine dependent functions for kernel setup * * This file needs a lot of work. *