From owner-svn-src-projects@FreeBSD.ORG Mon Jan 26 06:13:09 2009 Return-Path: Delivered-To: svn-src-projects@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id BE204106564A; Mon, 26 Jan 2009 06:13:09 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id ADBD88FC18; Mon, 26 Jan 2009 06:13:09 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n0Q6D9sS038607; Mon, 26 Jan 2009 06:13:09 GMT (envelope-from gonzo@svn.freebsd.org) Received: (from gonzo@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n0Q6D96q038605; Mon, 26 Jan 2009 06:13:09 GMT (envelope-from gonzo@svn.freebsd.org) Message-Id: <200901260613.n0Q6D96q038605@svn.freebsd.org> From: Oleksandr Tymoshenko Date: Mon, 26 Jan 2009 06:13:09 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r187705 - projects/mips/sys/mips/atheros X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 26 Jan 2009 06:13:10 -0000 Author: gonzo Date: Mon Jan 26 06:13:09 2009 New Revision: 187705 URL: http://svn.freebsd.org/changeset/base/187705 Log: - Rename RESET-related registers - Add PCI registers Modified: projects/mips/sys/mips/atheros/ar71xx_machdep.c projects/mips/sys/mips/atheros/ar71xxreg.h Modified: projects/mips/sys/mips/atheros/ar71xx_machdep.c ============================================================================== --- projects/mips/sys/mips/atheros/ar71xx_machdep.c Mon Jan 26 05:44:40 2009 (r187704) +++ projects/mips/sys/mips/atheros/ar71xx_machdep.c Mon Jan 26 06:13:09 2009 (r187705) @@ -74,7 +74,7 @@ platform_reset(void) { uint32_t reg = ATH_READ_REG(AR71XX_RST_RESET); - ATH_WRITE_REG(AR71XX_RST_RESET, reg | RST_RESET_FULL_CHIP_RESET); + ATH_WRITE_REG(AR71XX_RST_RESET, reg | RST_RESET_FULL_CHIP); /* Wait for reset */ while(1) ; Modified: projects/mips/sys/mips/atheros/ar71xxreg.h ============================================================================== --- projects/mips/sys/mips/atheros/ar71xxreg.h Mon Jan 26 05:44:40 2009 (r187704) +++ projects/mips/sys/mips/atheros/ar71xxreg.h Mon Jan 26 06:13:09 2009 (r187705) @@ -32,9 +32,75 @@ #define ATH_WRITE_REG(reg, val) \ *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val) -#define AR71XX_UART_ADDR 0x18020000 +/* PCI region */ +#define AR71XX_PCI_MEM_BASE 0x10000000 +/* + * PCI mem windows is 0x08000000 bytes long but we exclude control + * region from the resource manager + */ +#define AR71XX_PCI_MEM_SIZE 0x07000000 +#define AR71XX_PCI_IRQ_START 0 +#define AR71XX_PCI_IRQ_END 2 + +/* PCI config registers */ +#define AR71XX_PCI_LCONF_CMD 0x17010000 +#define PCI_LCONF_CMD_READ 0x00000000 +#define PCI_LCONF_CMD_WRITE 0x00010000 +#define AR71XX_PCI_LCONF_WRITE_DATA 0x17010004 +#define AR71XX_PCI_LCONF_READ_DATA 0x17010008 +#define AR71XX_PCI_CONF_ADDR 0x1701000C +#define AR71XX_PCI_CONF_CMD 0x17010010 +#define PCI_CONF_CMD_READ 0x0000000A +#define PCI_CONF_CMD_WRITE 0x0000000B +#define AR71XX_PCI_CONF_WRITE_DATA 0x17010014 +#define AR71XX_PCI_CONF_READ_DATA 0x17010018 +#define AR71XX_PCI_ERROR 0x1701001C +#define AR71XX_PCI_ERROR_ADDR 0x17010020 +#define AR71XX_PCI_AHB_ERROR 0x17010024 +#define AR71XX_PCI_AHB_ERROR_ADDR 0x17010028 + +/* APB region */ +/* DDR registers */ +#define AR71XX_DDR_CONFIG 0x18000000 +#define AR71XX_DDR_CONFIG2 0x18000004 +#define AR71XX_DDR_MODE_REGISTER 0x18000008 +#define AR71XX_DDR_EXT_MODE_REGISTER 0x1800000C +#define AR71XX_DDR_CONTROL 0x18000010 +#define AR71XX_DDR_REFRESH 0x18000014 +#define AR71XX_DDR_RD_DATA_THIS_CYCLE 0x18000018 +#define AR71XX_TAP_CONTROL0 0x1800001C +#define AR71XX_TAP_CONTROL1 0x18000020 +#define AR71XX_TAP_CONTROL2 0x18000024 +#define AR71XX_TAP_CONTROL3 0x18000028 +#define AR71XX_PCI_WINDOW0 0x1800007C +#define AR71XX_PCI_WINDOW1 0x18000080 +#define AR71XX_PCI_WINDOW2 0x18000084 +#define AR71XX_PCI_WINDOW3 0x18000088 +#define AR71XX_PCI_WINDOW4 0x1800008C +#define AR71XX_PCI_WINDOW5 0x18000090 +#define AR71XX_PCI_WINDOW6 0x18000094 +#define AR71XX_PCI_WINDOW7 0x18000098 +#define AR71XX_WB_FLUSH_GE0 0x1800009C +#define AR71XX_WB_FLUSH_GE1 0x180000A0 +#define AR71XX_WB_FLUSH_USB 0x180000A4 +#define AR71XX_WB_FLUSH_PCI 0x180000A8 + +/* + * Values for PCI_WINDOW_X registers + */ +#define PCI_WINDOW0_ADDR 0x10000000 +#define PCI_WINDOW1_ADDR 0x11000000 +#define PCI_WINDOW2_ADDR 0x12000000 +#define PCI_WINDOW3_ADDR 0x13000000 +#define PCI_WINDOW4_ADDR 0x14000000 +#define PCI_WINDOW5_ADDR 0x15000000 +#define PCI_WINDOW6_ADDR 0x16000000 +#define PCI_WINDOW7_ADDR 0x17000000 +/* This value enables acces to PCI config registers */ +#define PCI_WINDOW7_CONF_ADDR 0x07000000 + +#define AR71XX_UART_ADDR 0x18020000 -/* APB registers */ /* * APB interrupt status and mask register and interrupt bit numbers for */ @@ -49,8 +115,14 @@ #define MISC_INTR_OHCI 6 #define MISC_INTR_DMA 7 +#define AR71XX_PCI_INTR_STATUS 0x18060018 +#define AR71XX_PCI_INTR_MASK 0x1806001C +#define PCI_INTR_CORE (1 << 4) + #define AR71XX_RST_RESET 0x18060024 -#define RST_RESET_CPU_COLD_RESET (1 << 20) /* Cold reset */ -#define RST_RESET_FULL_CHIP_RESET (1 << 24) /* Same as pulling +#define RST_RESET_PCI_CORE (1 << 0) +#define RST_RESET_PCI_BUS (1 << 1) +#define RST_RESET_CPU_COLD (1 << 20) /* Cold reset */ +#define RST_RESET_FULL_CHIP (1 << 24) /* Same as pulling the reset pin */ #endif /* _AR71XX_REG_H_ */