From owner-p4-projects@FreeBSD.ORG Thu Jan 31 15:37:27 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 4279416A418; Thu, 31 Jan 2008 15:37:27 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id E323416A46B for ; Thu, 31 Jan 2008 15:37:26 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id C6B3A13C44B for ; Thu, 31 Jan 2008 15:37:26 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.1/8.14.1) with ESMTP id m0VFbQPQ047718 for ; Thu, 31 Jan 2008 15:37:26 GMT (envelope-from rrs@cisco.com) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.1/8.14.1/Submit) id m0VFbPDa047715 for perforce@freebsd.org; Thu, 31 Jan 2008 15:37:25 GMT (envelope-from rrs@cisco.com) Date: Thu, 31 Jan 2008 15:37:25 GMT Message-Id: <200801311537.m0VFbPDa047715@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to rrs@cisco.com using -f From: "Randall R. Stewart" To: Perforce Change Reviews Cc: Subject: PERFORCE change 134549 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Jan 2008 15:37:27 -0000 http://perforce.freebsd.org/chv.cgi?CH=134549 Change 134549 by rrs@rrs-mips2-jnpr on 2008/01/31 15:37:06 Pulls over the TARGET_OCTEON 128 bit cache line entry stuff Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/include/cache_mipsNN.h#2 edit .. //depot/projects/mips2-jnpr/src/sys/mips/include/cpufunc.h#6 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/cache.c#2 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/cache_mipsNN.c#2 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/include/cache_mipsNN.h#2 (text+ko) ==== @@ -53,3 +53,13 @@ void mipsNN_pdcache_inv_range_32(vm_offset_t, vm_size_t); void mipsNN_pdcache_wb_range_16(vm_offset_t, vm_size_t); void mipsNN_pdcache_wb_range_32(vm_offset_t, vm_size_t); +#ifdef TARGET_OCTEON +void mipsNN_icache_sync_all_128(void); +void mipsNN_icache_sync_range_128(vm_offset_t, vm_size_t); +void mipsNN_icache_sync_range_index_128(vm_offset_t, vm_size_t); +void mipsNN_pdcache_wbinv_all_128(void); +void mipsNN_pdcache_wbinv_range_128(vm_offset_t, vm_size_t); +void mipsNN_pdcache_wbinv_range_index_128(vm_offset_t, vm_size_t); +void mipsNN_pdcache_inv_range_128(vm_offset_t, vm_size_t); +void mipsNN_pdcache_wb_range_128(vm_offset_t, vm_size_t); +#endif ==== //depot/projects/mips2-jnpr/src/sys/mips/include/cpufunc.h#6 (text+ko) ==== @@ -183,6 +183,18 @@ mips_barrier(); \ } struct __hack +#ifdef TARGET_OCTEON +static __inline void mips_sync_icache (void) +{ + __asm __volatile ( + ".set mips64\n" + ".word 0x041f0000\n" + "nop\n" + ".set mips0\n" + : : ); +} +#endif + MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE); MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG); MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT); ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/cache.c#2 (text+ko) ==== @@ -51,6 +51,16 @@ mips_cache_ops.mco_icache_sync_range_index = mipsNN_icache_sync_range_index_32; break; +#ifdef TARGET_OCTEON + case 128: + mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_128; + mips_cache_ops.mco_icache_sync_range = + mipsNN_icache_sync_range_128; + mips_cache_ops.mco_icache_sync_range_index = + mipsNN_icache_sync_range_index_128; + break; +#endif + #ifdef MIPS_DISABLE_L1_CACHE case 0: mips_cache_ops.mco_icache_sync_all = cache_noop; @@ -96,6 +106,23 @@ mips_cache_ops.mco_intern_pdcache_wb_range = mipsNN_pdcache_wb_range_32; break; +#ifdef TARGET_OCTEON + case 128: + mips_cache_ops.mco_pdcache_wbinv_all = + mips_cache_ops.mco_intern_pdcache_wbinv_all = + mipsNN_pdcache_wbinv_all_128; + mips_cache_ops.mco_pdcache_wbinv_range = + mipsNN_pdcache_wbinv_range_128; + mips_cache_ops.mco_pdcache_wbinv_range_index = + mips_cache_ops.mco_intern_pdcache_wbinv_range_index = + mipsNN_pdcache_wbinv_range_index_128; + mips_cache_ops.mco_pdcache_inv_range = + mipsNN_pdcache_inv_range_128; + mips_cache_ops.mco_pdcache_wb_range = + mips_cache_ops.mco_intern_pdcache_wb_range = + mipsNN_pdcache_wb_range_128; + break; +#endif #ifdef MIPS_DISABLE_L1_CACHE case 0: mips_cache_ops.mco_pdcache_wbinv_all = cache_noop; ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/cache_mipsNN.c#2 (text+ko) ==== @@ -56,6 +56,13 @@ #define SYNC __asm volatile("sync") #endif +#ifdef TARGET_OCTEON +#define SYNCI mips_sync_icache(); +#else +#define SYNCI +#endif + + __asm(".set mips32"); static int picache_size; @@ -545,3 +552,54 @@ SYNC; } + + +#ifdef TARGET_OCTEON + +void +mipsNN_icache_sync_all_128(void) +{ + SYNCI +} + +void +mipsNN_icache_sync_range_128(vm_offset_t va, vm_size_t size) +{ + SYNC; +} + +void +mipsNN_icache_sync_range_index_128(vm_offset_t va, vm_size_t size) +{ +} + + +void +mipsNN_pdcache_wbinv_all_128(void) +{ +} + + +void +mipsNN_pdcache_wbinv_range_128(vm_offset_t va, vm_size_t size) +{ + SYNC; +} + +void +mipsNN_pdcache_wbinv_range_index_128(vm_offset_t va, vm_size_t size) +{ +} + +void +mipsNN_pdcache_inv_range_128(vm_offset_t va, vm_size_t size) +{ +} + +void +mipsNN_pdcache_wb_range_128(vm_offset_t va, vm_size_t size) +{ + SYNC; +} + +#endif