Date: Wed, 22 Sep 2004 16:35:54 +0200 From: Bruno Ducrot <ducrot@poupinou.org> To: freebsd-mobile@freebsd.org Subject: Re: [speedstep] testers wanted (Jochen Gensch) Message-ID: <20040922143554.GX16132@poupinou.org> In-Reply-To: <20040922070324.GA4985@empiric.icir.org> References: <200409210949.25803.kjelderg@sponge.dyndns.org> <20040921151934.GW16132@poupinou.org> <20040922070324.GA4985@empiric.icir.org>
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Hi, On Wed, Sep 22, 2004 at 12:03:25AM -0700, Bruce M Simpson wrote: > Testing on an IBM T40: > > ichist0: <Intel ICH4m LPC bridge> on motherboard > > Loads OK. sysctl dev.ichist: > > dev.ichist.0.%desc: Intel ICH4m LPC bridge > dev.ichist.0.%driver: ichist > dev.ichist.0.%parent: nexus0 > dev.ichist.0.speedstep: 0 > > However, if I try to set the status: > > empiric:~ % s sysctl dev.ichist.0.speedstep=1 > dev.ichist.0.speedstep: 0 -> 0 > > ...nothing happens. Likely the BIOS don't set access to the SS_CTL IO register at POST either because it do not detect a valid processor (PIII-M or P4-M), or because it has set an SMI handler in order to change frequency/voltage. There is also a good luck that a single call to the SMI may change this situation (via either an intel propritary interface for early PIII-M, or from ACPI for newer). Under Linux, we set unconditionnaly the access to this IO because at the time we wrote this one, we didn't knew how to correctly call the bios (much more due to non access to documentation), but we knew how to detect if a processor is speedstep capable (well, actually there is still some little trouble with earlier PIII). -- Bruno Ducrot -- Which is worse: ignorance or apathy? -- Don't know. Don't care.
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