From owner-svn-src-all@FreeBSD.ORG Sat Nov 19 14:14:35 2011 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id C8DC4106566C; Sat, 19 Nov 2011 14:14:35 +0000 (UTC) (envelope-from jchandra@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 9EBED8FC08; Sat, 19 Nov 2011 14:14:35 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id pAJEEZI8046745; Sat, 19 Nov 2011 14:14:35 GMT (envelope-from jchandra@svn.freebsd.org) Received: (from jchandra@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id pAJEEZGR046743; Sat, 19 Nov 2011 14:14:35 GMT (envelope-from jchandra@svn.freebsd.org) Message-Id: <201111191414.pAJEEZGR046743@svn.freebsd.org> From: "Jayachandran C." Date: Sat, 19 Nov 2011 14:14:35 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r227724 - head/sys/mips/mips X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 19 Nov 2011 14:14:35 -0000 Author: jchandra Date: Sat Nov 19 14:14:35 2011 New Revision: 227724 URL: http://svn.freebsd.org/changeset/base/227724 Log: Fixup cache flush definitions for XLP mco_icache_sync_range was earlier set to mipsNN_icache_sync_range_index_32 which is not necessary, revert this. Also, the data cache is coherent so write back is not really needed. This change is experimental. Modified: head/sys/mips/mips/cache.c Modified: head/sys/mips/mips/cache.c ============================================================================== --- head/sys/mips/mips/cache.c Sat Nov 19 14:10:16 2011 (r227723) +++ head/sys/mips/mips/cache.c Sat Nov 19 14:14:35 2011 (r227724) @@ -101,13 +101,8 @@ mips_config_cache(struct mips_cpuinfo * break; case 32: mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_32; -#ifdef CPU_NLM - mips_cache_ops.mco_icache_sync_range = - mipsNN_icache_sync_range_index_32; -#else mips_cache_ops.mco_icache_sync_range = mipsNN_icache_sync_range_32; -#endif mips_cache_ops.mco_icache_sync_range_index = mipsNN_icache_sync_range_index_32; break; @@ -155,18 +150,23 @@ mips_config_cache(struct mips_cpuinfo * mips_cache_ops.mco_pdcache_wbinv_all = mips_cache_ops.mco_intern_pdcache_wbinv_all = mipsNN_pdcache_wbinv_all_32; -#ifdef CPU_NLM - mips_cache_ops.mco_pdcache_wbinv_range = - mipsNN_pdcache_wbinv_range_index_32; +#if defined(CPU_RMI) || defined(CPU_NLM) + mips_cache_ops.mco_pdcache_wbinv_range = cache_noop; #else mips_cache_ops.mco_pdcache_wbinv_range = mipsNN_pdcache_wbinv_range_32; #endif +#if defined(CPU_RMI) || defined(CPU_NLM) + mips_cache_ops.mco_pdcache_wbinv_range_index = + mips_cache_ops.mco_intern_pdcache_wbinv_range_index = cache_noop; + mips_cache_ops.mco_pdcache_inv_range = cache_noop; +#else mips_cache_ops.mco_pdcache_wbinv_range_index = mips_cache_ops.mco_intern_pdcache_wbinv_range_index = mipsNN_pdcache_wbinv_range_index_32; mips_cache_ops.mco_pdcache_inv_range = mipsNN_pdcache_inv_range_32; +#endif #if defined(CPU_RMI) || defined(CPU_NLM) mips_cache_ops.mco_pdcache_wb_range = mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop;