Date: Tue, 7 Jan 2020 20:13:31 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r356469 - in stable/12/contrib/llvm-project: lld/ELF/Arch llvm/lib/Target/RISCV llvm/lib/Target/RISCV/MCTargetDesc Message-ID: <202001072013.007KDViQ009883@repo.freebsd.org>
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Author: dim Date: Tue Jan 7 20:13:31 2020 New Revision: 356469 URL: https://svnweb.freebsd.org/changeset/base/356469 Log: MFC r356329: Merge commit 41449c58c from llvm git (by Roger Ferrer Ibanez): [RISCV] Fix evaluation of %pcrel_lo The following testcase function: .Lpcrel_label1: auipc a0, %pcrel_hi(other_function) addi a1, a0, %pcrel_lo(.Lpcrel_label1) .p2align 2 # Causes a new fragment to be emitted .type other_function,@function other_function: ret exposes an odd behaviour in which only the %pcrel_hi relocation is evaluated but not the %pcrel_lo. $ llvm-mc -triple riscv64 -filetype obj t.s | llvm-objdump -d -r - <stdin>: file format ELF64-riscv Disassembly of section .text: 0000000000000000 function: 0: 17 05 00 00 auipc a0, 0 4: 93 05 05 00 mv a1, a0 0000000000000004: R_RISCV_PCREL_LO12_I other_function+4 0000000000000008 other_function: 8: 67 80 00 00 ret The reason seems to be that in RISCVAsmBackend::shouldForceRelocation we only consider the fragment but in RISCVMCExpr::evaluatePCRelLo we consider the section. This usually works but there are cases where the section may still be the same but the fragment may be another one. In that case we end forcing a %pcrel_lo relocation without any %pcrel_hi. This patch makes RISCVAsmBackend::shouldForceRelocation use the section, if any, to determine if the relocation must be forced or not. Differential Revision: https://reviews.llvm.org/D60657 This is a prerequisite for building and linking hard- and soft-float riscv worlds with clang and lld. Requested by: jhb MFC r356330: Merge commit da7b129b1 from llvm git (by James Clarke): [RISCV] Don't force Local Exec TLS for non-PIC Summary: Forcing Local Exec TLS requires the use of copy relocations. Copy relocations need special handling in the runtime linker when being used against TLS symbols, which is present in glibc, but not in FreeBSD nor musl, and so cannot be relied upon. Moreover, copy relocations are a hack that embed the size of an object in the ABI when it otherwise wouldn't be, and break protected symbols (which are expected to be DSO local), whilst also wasting space, thus they should be avoided whenever possible. As discussed in D70398, RISC-V should move away from forcing Local Exec, and instead use Initial Exec like other targets, with possible linker relaxation to follow. The RISC-V GCC maintainers also intend to adopt this more-conventional behaviour (see https://github.com/riscv/riscv-elf-psabi-doc/issues/122). Reviewers: asb, MaskRay Reviewed By: MaskRay Subscribers: emaste, krytarowski, hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, llvm-commits, bsdjhb Tags: #llvm Differential Revision: https://reviews.llvm.org/D70649 This is a prerequisite for building and linking hard- and soft-float riscv worlds with clang and lld. Requested by: jhb MFC r356331: Merge commit c6b09bff5 from llvm git (by Luís Marques): [RISCV] Fix wrong CFI directives Summary: Removes CFI CFA directives that could incorrectly propagate beyond the basic block they were inteded for. Specifically it removes the epilogue CFI directives. See the branch_and_tail_call test for an example of the issue. Should fix the stack unwinding issues caused by the incorrect directives. Reviewers: asb, lenary, shiva0217 Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D69723 This is a prerequisite for building and linking hard- and soft-float riscv worlds with clang and lld. Requested by: jhb MFC r356332: Merge commit d7be3eab5 from llvm git (by Luís Marques): [RISCV] Handle fcopysign(f32, f64) and fcopysign(f64, f32) Summary: Adds tablegen patterns to explicitly handle fcopysign where the magnitude and sign arguments have different types, due to the sign value casts being removed the by DAGCombiner. Support for RV32IF follows in a separate commit. Adds tests for all relevant scenarios except RV32IF. Reviewers: lenary Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D70678 This is a prerequisite for building and linking hard- and soft-float riscv worlds with clang and lld. Requested by: jhb MFC r356333: Merge commit 189b7393d from llvm git (by John Baldwin): [lld][RISCV] Use an e_flags of 0 if there are only binary input files. Summary: If none of the input files are ELF object files (for example, when generating an object file from a single binary input file via "-b binary"), use a fallback value for the ELF header flags instead of crashing with an assertion failure. Reviewers: MaskRay, ruiu, espindola Reviewed By: MaskRay, ruiu Subscribers: kevans, grimar, emaste, arichardson, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits, jrtc27 Tags: #llvm Differential Revision: https://reviews.llvm.org/D71101 This is a prerequisite for building and linking hard- and soft-float riscv worlds with clang and lld. Requested by: jhb Modified: stable/12/contrib/llvm-project/lld/ELF/Arch/RISCV.cpp stable/12/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp stable/12/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp stable/12/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.cpp stable/12/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoD.td Directory Properties: stable/12/ (props changed) stable/12/contrib/llvm-project/lld/ (props changed) stable/12/contrib/llvm-project/llvm/ (props changed) Modified: stable/12/contrib/llvm-project/lld/ELF/Arch/RISCV.cpp ============================================================================== --- stable/12/contrib/llvm-project/lld/ELF/Arch/RISCV.cpp Tue Jan 7 20:09:58 2020 (r356468) +++ stable/12/contrib/llvm-project/lld/ELF/Arch/RISCV.cpp Tue Jan 7 20:13:31 2020 (r356469) @@ -105,7 +105,10 @@ static uint32_t getEFlags(InputFile *f) { } uint32_t RISCV::calcEFlags() const { - assert(!objectFiles.empty()); + // If there are only binary input files (from -b binary), use a + // value of 0 for the ELF header flags. + if (objectFiles.empty()) + return 0; uint32_t target = getEFlags(objectFiles.front()); Modified: stable/12/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp ============================================================================== --- stable/12/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp Tue Jan 7 20:09:58 2020 (r356468) +++ stable/12/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp Tue Jan 7 20:13:31 2020 (r356469) @@ -64,10 +64,14 @@ bool RISCVAsmBackend::shouldForceRelocation(const MCAs case RISCV::fixup_riscv_tls_gd_hi20: ShouldForce = true; break; - case RISCV::fixup_riscv_pcrel_hi20: - ShouldForce = T->getValue()->findAssociatedFragment() != - Fixup.getValue()->findAssociatedFragment(); + case RISCV::fixup_riscv_pcrel_hi20: { + MCFragment *TFragment = T->getValue()->findAssociatedFragment(); + MCFragment *FixupFragment = Fixup.getValue()->findAssociatedFragment(); + assert(FixupFragment && "We should have a fragment for this fixup"); + ShouldForce = + !TFragment || TFragment->getParent() != FixupFragment->getParent(); break; + } } break; } Modified: stable/12/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp ============================================================================== --- stable/12/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp Tue Jan 7 20:09:58 2020 (r356468) +++ stable/12/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp Tue Jan 7 20:13:31 2020 (r356469) @@ -205,7 +205,6 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction MachineFrameInfo &MFI = MF.getFrameInfo(); auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>(); DebugLoc DL = MBBI->getDebugLoc(); - const RISCVInstrInfo *TII = STI.getInstrInfo(); unsigned FPReg = getFPReg(STI); unsigned SPReg = getSPReg(STI); @@ -226,47 +225,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction MachineInstr::FrameDestroy); } - if (hasFP(MF)) { - // To find the instruction restoring FP from stack. - for (auto &I = LastFrameDestroy; I != MBBI; ++I) { - if (I->mayLoad() && I->getOperand(0).isReg()) { - unsigned DestReg = I->getOperand(0).getReg(); - if (DestReg == FPReg) { - // If there is frame pointer, after restoring $fp registers, we - // need adjust CFA to ($sp - FPOffset). - // Emit ".cfi_def_cfa $sp, -FPOffset" - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa( - nullptr, RI->getDwarfRegNum(SPReg, true), -FPOffset)); - BuildMI(MBB, std::next(I), DL, - TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex); - break; - } - } - } - } - - // Add CFI directives for callee-saved registers. - const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); - // Iterate over list of callee-saved registers and emit .cfi_restore - // directives. - for (const auto &Entry : CSI) { - unsigned Reg = Entry.getReg(); - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore( - nullptr, RI->getDwarfRegNum(Reg, true))); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex); - } - // Deallocate stack adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy); - - // After restoring $sp, we need to adjust CFA to $(sp + 0) - // Emit ".cfi_def_cfa_offset 0" - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex); } int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, Modified: stable/12/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.cpp ============================================================================== --- stable/12/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.cpp Tue Jan 7 20:09:58 2020 (r356468) +++ stable/12/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.cpp Tue Jan 7 20:13:31 2020 (r356469) @@ -570,10 +570,7 @@ SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDV int64_t Offset = N->getOffset(); MVT XLenVT = Subtarget.getXLenVT(); - // Non-PIC TLS lowering should always use the LocalExec model. - TLSModel::Model Model = isPositionIndependent() - ? getTargetMachine().getTLSModel(N->getGlobal()) - : TLSModel::LocalExec; + TLSModel::Model Model = getTargetMachine().getTLSModel(N->getGlobal()); SDValue Addr; switch (Model) { Modified: stable/12/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoD.td ============================================================================== --- stable/12/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoD.td Tue Jan 7 20:09:58 2020 (r356468) +++ stable/12/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoD.td Tue Jan 7 20:13:31 2020 (r356469) @@ -231,6 +231,9 @@ def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>; def : PatFpr64Fpr64<fcopysign, FSGNJ_D>; def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>; +def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2))>; +def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2, + 0b111))>; // fmadd: rs1 * rs2 + rs3 def : Pat<(fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),
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