From owner-p4-projects@FreeBSD.ORG Thu Jan 31 15:45:36 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 7902C16A420; Thu, 31 Jan 2008 15:45:36 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 2648416A41B for ; Thu, 31 Jan 2008 15:45:36 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 09B8013C4D5 for ; Thu, 31 Jan 2008 15:45:36 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.1/8.14.1) with ESMTP id m0VFjZ86048101 for ; Thu, 31 Jan 2008 15:45:35 GMT (envelope-from rrs@cisco.com) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.1/8.14.1/Submit) id m0VFjZqT048098 for perforce@freebsd.org; Thu, 31 Jan 2008 15:45:35 GMT (envelope-from rrs@cisco.com) Date: Thu, 31 Jan 2008 15:45:35 GMT Message-Id: <200801311545.m0VFjZqT048098@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to rrs@cisco.com using -f From: "Randall R. Stewart" To: Perforce Change Reviews Cc: Subject: PERFORCE change 134551 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Jan 2008 15:45:36 -0000 http://perforce.freebsd.org/chv.cgi?CH=134551 Change 134551 by rrs@rrs-mips2-jnpr on 2008/01/31 15:44:56 one more change for the octeon cpu.c .. needs 128 byte cache lines Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips/cpu.c#8 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/cpu.c#8 (text+ko) ==== @@ -105,6 +105,15 @@ cpuinfo->l1.dc_linesize = tmp; cpuinfo->l1.dc_nways = (((cfg1 & MIPS_CONFIG1_DA_MASK) >> MIPS_CONFIG1_DA_SHIFT)) + 1; cpuinfo->l1.dc_nsets = 1 << (((cfg1 & MIPS_CONFIG1_DS_MASK) >> MIPS_CONFIG1_DS_SHIFT) + 6); +#ifdef TARGET_OCTEON + /* + * Octeon does 128 byte line-size. But Config-Sel1 doesn't show + * 128 line-size, 1 Set, 64 ways. + */ + cpuinfo->l1.dc_linesize = 128; + cpuinfo->l1.dc_nsets = 1; + cpuinfo->l1.dc_nways = 64; +#endif cpuinfo->l1.dc_size = cpuinfo->l1.dc_linesize * cpuinfo->l1.dc_nsets * cpuinfo->l1.dc_nways; }