Date: Thu, 24 May 2001 12:53:16 +0300 From: Ruslan Ermilov <ru@FreeBSD.org> To: Mike Smith <msmith@FreeBSD.org> Cc: arch@FreeBSD.org Subject: mlxio.h (was: Re: Where to put include files) Message-ID: <20010524125316.E79111@sunbay.com> In-Reply-To: <Pine.BSF.4.33.0105181137390.27157-100000@herring.nlsystems.com>; from dfr@nlsystems.com on Fri, May 18, 2001 at 11:39:14AM %2B0100 References: <200105171600.f4HG0Pl05438@billy-club.village.org> <Pine.BSF.4.33.0105181137390.27157-100000@herring.nlsystems.com>
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--+HP7ph2BbKc20aGI
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On Fri, May 18, 2001 at 11:39:14AM +0100, Doug Rabson wrote:
> On Thu, 17 May 2001, Warner Losh wrote:
>
> > In message <200105171233.f4HCXhb62786@hak.lan.Awfulhak.org> Brian
> > Somers writes:
> > : Solaris calls it's ioctl files /usr/include/sys/<driver>_io.h so I'd
> > : spell digiio.h /usr/include/sys/digi_io.h.
> >
> > Actually, the more I think about it, the more I like putting it in
> > /usr/include/sys/fooio.h. We have lots of other files there now. The
> > down side to this approach is that it breaks up the driver sources
> > that we've been trying to concentrate into sys/dev/foo/* (or
> > introduces asymetry such that you can't just toss in a -I/sys and have
> > the same tree that gets stuck under /usr/include).
>
> I quite like the fact that the programming interface <sys/fooio.h> is
> separated from the driver implementation. There is less chance that the
> driver writer will expose irrelavent implementation details in the API,
> which in turn makes for a more stable ABI.
>
Hi!
What I propose is to make mlxio.h self-contained to be suitable
for userland, and move it to /sys/sys where it belongs, and to
get rid of that bogus -I line in mlxcontrol/Makefile.
The attached patch merely moves the (non-kernel) part of mlxreg.h
into mlxio.h (which is IMHO belongs to API anyway), unconnects
mlxreg.h from userland, and removes _KERNEL conditional from
mlxreg.h.
If this looks acceptable, the next step would be:
1. repo-copy mlxio.h to /sys/sys (so that it gets installed into
/usr/include/sys)
2. fix mlxcontrol's #include's for the new location
3. remove CFLAGS+=-I${.CURDIR}/../../sys from mlxcontrol/Makefile.
I've verified that both mlx module and mlxcontrol build OK with
this patch.
Cheers,
--
Ruslan Ermilov Oracle Developer/DBA,
ru@sunbay.com Sunbay Software AG,
ru@FreeBSD.org FreeBSD committer,
+380.652.512.251 Simferopol, Ukraine
http://www.FreeBSD.org The Power To Serve
http://www.oracle.com Enabling The Information Age
--+HP7ph2BbKc20aGI
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Index: sys/dev/mlx/mlxio.h
===================================================================
RCS file: /home/ncvs/src/sys/dev/mlx/mlxio.h,v
retrieving revision 1.3
diff -u -r1.3 mlxio.h
--- sys/dev/mlx/mlxio.h 2000/04/11 02:52:44 1.3
+++ sys/dev/mlx/mlxio.h 2001/05/24 09:36:29
@@ -95,3 +95,332 @@
#define MLX_REBUILDASYNC _IOWR('M', 5, struct mlx_rebuild_request)
#define MLX_REBUILDSTAT _IOR ('M', 6, struct mlx_rebuild_status)
#define MLX_GET_SYSDRIVE _IOWR('M', 7, int)
+
+
+#define MLX_BLKSIZE 512 /* fixed feature */
+
+/*
+ * Selected command codes.
+ */
+#define MLX_CMD_ENQUIRY_OLD 0x05
+#define MLX_CMD_ENQUIRY 0x53
+#define MLX_CMD_ENQUIRY2 0x1c
+#define MLX_CMD_ENQSYSDRIVE 0x19
+#define MLX_CMD_READSG 0xb6
+#define MLX_CMD_WRITESG 0xb7
+#define MLX_CMD_READSG_OLD 0x82
+#define MLX_CMD_WRITESG_OLD 0x83
+#define MLX_CMD_FLUSH 0x0a
+#define MLX_CMD_LOGOP 0x72
+#define MLX_CMD_REBUILDASYNC 0x16
+#define MLX_CMD_CHECKASYNC 0x1e
+#define MLX_CMD_REBUILDSTAT 0x0c
+#define MLX_CMD_STOPCHANNEL 0x13
+#define MLX_CMD_STARTCHANNEL 0x12
+#define MLX_CMD_READ_CONFIG 0x4e
+#define MLX_CMD_DIRECT_CDB 0x04
+#define MLX_CMD_DEVICE_STATE 0x50
+
+
+/*
+ * Scatter-gather list format, type 1, kind 00.
+ */
+struct mlx_sgentry
+{
+ u_int32_t sg_addr;
+ u_int32_t sg_count;
+} __attribute__ ((packed));
+
+/*
+ * Command result buffers, as placed in system memory by the controller.
+ */
+
+struct mlx_enquiry_old /* MLX_CMD_ENQUIRY_OLD */
+{
+ u_int8_t me_num_sys_drvs;
+ u_int8_t res1[3];
+ u_int32_t me_drvsize[8];
+ u_int16_t me_flash_age;
+ u_int8_t me_status_flags;
+ u_int8_t me_free_state_change_count;
+ u_int8_t me_fwminor;
+ u_int8_t me_fwmajor;
+ u_int8_t me_rebuild_flag;
+ u_int8_t me_max_commands;
+ u_int8_t me_offline_sd_count;
+ u_int8_t res3;
+ u_int8_t me_critical_sd_count;
+ u_int8_t res4[3];
+ u_int8_t me_dead_count;
+ u_int8_t res5;
+ u_int8_t me_rebuild_count;
+ u_int8_t me_misc_flags;
+ struct
+ {
+ u_int8_t dd_targ;
+ u_int8_t dd_chan;
+ } __attribute__ ((packed)) me_dead[20];
+} __attribute__ ((packed));
+
+struct mlx_enquiry /* MLX_CMD_ENQUIRY */
+{
+ u_int8_t me_num_sys_drvs;
+ u_int8_t res1[3];
+ u_int32_t me_drvsize[32];
+ u_int16_t me_flash_age;
+ u_int8_t me_status_flags;
+#define MLX_ENQ_SFLAG_DEFWRERR (1<<0) /* deferred write error indicator */
+#define MLX_ENQ_SFLAG_BATTLOW (1<<1) /* battery low */
+ u_int8_t res2;
+ u_int8_t me_fwminor;
+ u_int8_t me_fwmajor;
+ u_int8_t me_rebuild_flag;
+ u_int8_t me_max_commands;
+ u_int8_t me_offline_sd_count;
+ u_int8_t res3;
+ u_int16_t me_event_log_seq_num;
+ u_int8_t me_critical_sd_count;
+ u_int8_t res4[3];
+ u_int8_t me_dead_count;
+ u_int8_t res5;
+ u_int8_t me_rebuild_count;
+ u_int8_t me_misc_flags;
+#define MLX_ENQ_MISC_BBU (1<<3) /* battery backup present */
+ struct
+ {
+ u_int8_t dd_targ;
+ u_int8_t dd_chan;
+ } __attribute__ ((packed)) me_dead[20];
+} __attribute__ ((packed));
+
+struct mlx_enquiry2 /* MLX_CMD_ENQUIRY2 */
+{
+ u_int32_t me_hardware_id;
+ u_int32_t me_firmware_id;
+ u_int32_t res1;
+ u_int8_t me_configured_channels;
+ u_int8_t me_actual_channels;
+ u_int8_t me_max_targets;
+ u_int8_t me_max_tags;
+ u_int8_t me_max_sys_drives;
+ u_int8_t me_max_arms;
+ u_int8_t me_max_spans;
+ u_int8_t res2;
+ u_int32_t res3;
+ u_int32_t me_mem_size;
+ u_int32_t me_cache_size;
+ u_int32_t me_flash_size;
+ u_int32_t me_nvram_size;
+ u_int16_t me_mem_type;
+ u_int16_t me_clock_speed;
+ u_int16_t me_mem_speed;
+ u_int16_t me_hardware_speed;
+ u_int8_t res4[12];
+ u_int16_t me_max_commands;
+ u_int16_t me_max_sg;
+ u_int16_t me_max_dp;
+ u_int16_t me_max_iod;
+ u_int16_t me_max_comb;
+ u_int8_t me_latency;
+ u_int8_t res5;
+ u_int8_t me_scsi_timeout;
+ u_int8_t res6;
+ u_int16_t me_min_freelines;
+ u_int8_t res7[8];
+ u_int8_t me_rate_const;
+ u_int8_t res8[11];
+ u_int16_t me_physblk;
+ u_int16_t me_logblk;
+ u_int16_t me_maxblk;
+ u_int16_t me_blocking_factor;
+ u_int16_t me_cacheline;
+ u_int8_t me_scsi_cap;
+ u_int8_t res9[5];
+ u_int16_t me_firmware_build;
+ u_int8_t me_fault_mgmt_type;
+ u_int8_t res10;
+ u_int32_t me_firmware_features;
+ u_int8_t res11[8];
+} __attribute__ ((packed));
+
+struct mlx_enq_sys_drive /* MLX_CMD_ENQSYSDRIVE returns an array of 32 of these */
+{
+ u_int32_t sd_size;
+ u_int8_t sd_state;
+ u_int8_t sd_raidlevel;
+ u_int16_t res1;
+} __attribute__ ((packed));
+
+struct mlx_eventlog_entry /* MLX_CMD_LOGOP/MLX_LOGOP_GET */
+{
+ u_int8_t el_type;
+ u_int8_t el_length;
+ u_char el_target:5;
+ u_char el_channel:3;
+ u_char el_lun:6;
+ u_char res1:2;
+ u_int16_t el_seqno;
+ u_char el_errorcode:7;
+ u_char el_valid:1;
+ u_int8_t el_segment;
+ u_char el_sensekey:4;
+ u_char res2:1;
+ u_char el_ILI:1;
+ u_char el_EOM:1;
+ u_char el_filemark:1;
+ u_int8_t el_information[4];
+ u_int8_t el_addsense;
+ u_int8_t el_csi[4];
+ u_int8_t el_asc;
+ u_int8_t el_asq;
+ u_int8_t res3[12];
+} __attribute__ ((packed));
+
+#define MLX_LOGOP_GET 0x00 /* operation codes for MLX_CMD_LOGOP */
+#define MLX_LOGMSG_SENSE 0x00 /* log message contents codes */
+
+struct mlx_rebuild_stat /* MLX_CMD_REBUILDSTAT */
+{
+ u_int32_t rb_drive;
+ u_int32_t rb_size;
+ u_int32_t rb_remaining;
+} __attribute__ ((packed));
+
+struct mlx_config2
+{
+ u_int16_t cf_flags1;
+#define MLX_CF2_ACTV_NEG (1<<1)
+#define MLX_CF2_NORSTRTRY (1<<7)
+#define MLX_CF2_STRGWRK (1<<8)
+#define MLX_CF2_HPSUPP (1<<9)
+#define MLX_CF2_NODISCN (1<<10)
+#define MLX_CF2_ARM (1<<13)
+#define MLX_CF2_OFM (1<<15)
+#define MLX_CF2_AEMI (MLX_CF2_ARM | MLX_CF2_OFM)
+ u_int8_t cf_oemid;
+ u_int8_t cf_oem_model;
+ u_int8_t cf_physical_sector;
+ u_int8_t cf_logical_sector;
+ u_int8_t cf_blockfactor;
+ u_int8_t cf_flags2;
+#define MLX_CF2_READAH (1<<0)
+#define MLX_CF2_BIOSDLY (1<<1)
+#define MLX_CF2_REASS1S (1<<4)
+#define MLX_CF2_FUAENABL (1<<6)
+#define MLX_CF2_R5ALLS (1<<7)
+ u_int8_t cf_rcrate;
+ u_int8_t cf_res1;
+ u_int8_t cf_blocks_per_cache_line;
+ u_int8_t cf_blocks_per_stripe;
+ u_int8_t cf_scsi_param_0;
+ u_int8_t cf_scsi_param_1;
+ u_int8_t cf_scsi_param_2;
+ u_int8_t cf_scsi_param_3;
+ u_int8_t cf_scsi_param_4;
+ u_int8_t cf_scsi_param_5;
+ u_int8_t cf_scsi_initiator_id;
+ u_int8_t cf_res2;
+ u_int8_t cf_startup_mode;
+ u_int8_t cf_simultaneous_spinup_devices;
+ u_int8_t cf_delay_between_spinups;
+ u_int8_t cf_res3;
+ u_int16_t cf_checksum;
+} __attribute__ ((packed));
+
+struct mlx_sys_drv_span
+{
+ u_int32_t sp_start_lba;
+ u_int32_t sp_nblks;
+ u_int8_t sp_arm[8];
+} __attribute__ ((packed));
+
+struct mlx_sys_drv
+{
+ u_int8_t sd_status;
+ u_int8_t sd_ext_status;
+ u_int8_t sd_mod1;
+ u_int8_t sd_mod2;
+ u_int8_t sd_raidlevel;
+#define MLX_SYS_DRV_WRITEBACK (1<<7)
+#define MLX_SYS_DRV_RAID0 0
+#define MLX_SYS_DRV_RAID1 1
+#define MLX_SYS_DRV_RAID3 3
+#define MLX_SYS_DRV_RAID5 5
+#define MLX_SYS_DRV_RAID6 6
+#define MLX_SYS_DRV_JBOD 7
+ u_int8_t sd_valid_arms;
+ u_int8_t sd_valid_spans;
+ u_int8_t sd_init_state;
+#define MLX_SYS_DRV_INITTED 0x81;
+ struct mlx_sys_drv_span sd_span[4];
+} __attribute__ ((packed));
+
+struct mlx_phys_drv
+{
+ u_int8_t pd_flags1;
+#define MLX_PHYS_DRV_PRESENT (1<<0)
+ u_int8_t pd_flags2;
+#define MLX_PHYS_DRV_OTHER 0x00
+#define MLX_PHYS_DRV_DISK 0x01
+#define MLX_PHYS_DRV_SEQUENTIAL 0x02
+#define MLX_PHYS_DRV_CDROM 0x03
+#define MLX_PHYS_DRV_FAST20 (1<<3)
+#define MLX_PHYS_DRV_SYNC (1<<4)
+#define MLX_PHYS_DRV_FAST (1<<5)
+#define MLX_PHYS_DRV_WIDE (1<<6)
+#define MLX_PHYS_DRV_TAG (1<<7)
+ u_int8_t pd_status;
+#define MLX_PHYS_DRV_DEAD 0x00
+#define MLX_PHYS_DRV_WRONLY 0x02
+#define MLX_PHYS_DRV_ONLINE 0x03
+#define MLX_PHYS_DRV_STANDBY 0x10
+ u_int8_t pd_res1;
+ u_int8_t pd_period;
+ u_int8_t pd_offset;
+ u_int32_t pd_config_size;
+} __attribute__ ((packed));
+
+struct mlx_core_cfg
+{
+ u_int8_t cc_num_sys_drives;
+ u_int8_t cc_res1[3];
+ struct mlx_sys_drv cc_sys_drives[32];
+ struct mlx_phys_drv cc_phys_drives[5 * 16];
+} __attribute__ ((packed));
+
+struct mlx_dcdb
+{
+ u_int8_t dcdb_target:4;
+ u_int8_t dcdb_channel:4;
+ u_int8_t dcdb_flags;
+#define MLX_DCDB_NO_DATA 0x00
+#define MLX_DCDB_DATA_IN 0x01
+#define MLX_DCDB_DATA_OUT 0x02
+#define MLX_DCDB_EARLY_STATUS (1<<2)
+#define MLX_DCDB_TIMEOUT_10S 0x10
+#define MLX_DCDB_TIMEOUT_60S 0x20
+#define MLX_DCDB_TIMEOUT_20M 0x30
+#define MLX_DCDB_TIMEOUT_24H 0x40
+#define MLX_DCDB_NO_AUTO_SENSE (1<<6)
+#define MLX_DCDB_DISCONNECT (1<<7)
+ u_int16_t dcdb_datasize;
+ u_int32_t dcdb_physaddr;
+ u_int8_t dcdb_cdb_length:4;
+ u_int8_t dcdb_datasize_high:4;
+ u_int8_t dcdb_sense_length;
+ u_int8_t dcdb_cdb[12];
+ u_int8_t dcdb_sense[64];
+ u_int8_t dcdb_status;
+ u_int8_t res1;
+} __attribute__ ((packed));
+
+struct mlx_bbtable_entry
+{
+ u_int32_t bbt_block_number;
+ u_int8_t bbt_extent;
+ u_int8_t res1;
+ u_int8_t bbt_entry_type;
+ u_int8_t bbt_system_drive:5;
+ u_int8_t res2:3;
+} __attribute__ ((packed));
+
Index: sys/dev/mlx/mlxreg.h
===================================================================
RCS file: /home/ncvs/src/sys/dev/mlx/mlxreg.h,v
retrieving revision 1.7
diff -u -r1.7 mlxreg.h
--- sys/dev/mlx/mlxreg.h 2000/04/11 02:52:45 1.7
+++ sys/dev/mlx/mlxreg.h 2001/05/24 09:36:29
@@ -26,32 +26,6 @@
* $FreeBSD: src/sys/dev/mlx/mlxreg.h,v 1.7 2000/04/11 02:52:45 msmith Exp $
*/
-#define MLX_BLKSIZE 512 /* fixed feature */
-
-/*
- * Selected command codes.
- */
-#define MLX_CMD_ENQUIRY_OLD 0x05
-#define MLX_CMD_ENQUIRY 0x53
-#define MLX_CMD_ENQUIRY2 0x1c
-#define MLX_CMD_ENQSYSDRIVE 0x19
-#define MLX_CMD_READSG 0xb6
-#define MLX_CMD_WRITESG 0xb7
-#define MLX_CMD_READSG_OLD 0x82
-#define MLX_CMD_WRITESG_OLD 0x83
-#define MLX_CMD_FLUSH 0x0a
-#define MLX_CMD_LOGOP 0x72
-#define MLX_CMD_REBUILDASYNC 0x16
-#define MLX_CMD_CHECKASYNC 0x1e
-#define MLX_CMD_REBUILDSTAT 0x0c
-#define MLX_CMD_STOPCHANNEL 0x13
-#define MLX_CMD_STARTCHANNEL 0x12
-#define MLX_CMD_READ_CONFIG 0x4e
-#define MLX_CMD_DIRECT_CDB 0x04
-#define MLX_CMD_DEVICE_STATE 0x50
-
-#ifdef _KERNEL
-
#define MLX_CFG_BASE0 0x10 /* first region */
#define MLX_CFG_BASE1 0x14 /* second region (type 3 only) */
@@ -190,312 +164,7 @@
#define MLX_V5_FWERROR_PEND (1<<2) /* firmware error pending */
-#endif /* _KERNEL */
-
/*
- * Scatter-gather list format, type 1, kind 00.
- */
-struct mlx_sgentry
-{
- u_int32_t sg_addr;
- u_int32_t sg_count;
-} __attribute__ ((packed));
-
-/*
- * Command result buffers, as placed in system memory by the controller.
- */
-
-struct mlx_enquiry_old /* MLX_CMD_ENQUIRY_OLD */
-{
- u_int8_t me_num_sys_drvs;
- u_int8_t res1[3];
- u_int32_t me_drvsize[8];
- u_int16_t me_flash_age;
- u_int8_t me_status_flags;
- u_int8_t me_free_state_change_count;
- u_int8_t me_fwminor;
- u_int8_t me_fwmajor;
- u_int8_t me_rebuild_flag;
- u_int8_t me_max_commands;
- u_int8_t me_offline_sd_count;
- u_int8_t res3;
- u_int8_t me_critical_sd_count;
- u_int8_t res4[3];
- u_int8_t me_dead_count;
- u_int8_t res5;
- u_int8_t me_rebuild_count;
- u_int8_t me_misc_flags;
- struct
- {
- u_int8_t dd_targ;
- u_int8_t dd_chan;
- } __attribute__ ((packed)) me_dead[20];
-} __attribute__ ((packed));
-
-struct mlx_enquiry /* MLX_CMD_ENQUIRY */
-{
- u_int8_t me_num_sys_drvs;
- u_int8_t res1[3];
- u_int32_t me_drvsize[32];
- u_int16_t me_flash_age;
- u_int8_t me_status_flags;
-#define MLX_ENQ_SFLAG_DEFWRERR (1<<0) /* deferred write error indicator */
-#define MLX_ENQ_SFLAG_BATTLOW (1<<1) /* battery low */
- u_int8_t res2;
- u_int8_t me_fwminor;
- u_int8_t me_fwmajor;
- u_int8_t me_rebuild_flag;
- u_int8_t me_max_commands;
- u_int8_t me_offline_sd_count;
- u_int8_t res3;
- u_int16_t me_event_log_seq_num;
- u_int8_t me_critical_sd_count;
- u_int8_t res4[3];
- u_int8_t me_dead_count;
- u_int8_t res5;
- u_int8_t me_rebuild_count;
- u_int8_t me_misc_flags;
-#define MLX_ENQ_MISC_BBU (1<<3) /* battery backup present */
- struct
- {
- u_int8_t dd_targ;
- u_int8_t dd_chan;
- } __attribute__ ((packed)) me_dead[20];
-} __attribute__ ((packed));
-
-struct mlx_enquiry2 /* MLX_CMD_ENQUIRY2 */
-{
- u_int32_t me_hardware_id;
- u_int32_t me_firmware_id;
- u_int32_t res1;
- u_int8_t me_configured_channels;
- u_int8_t me_actual_channels;
- u_int8_t me_max_targets;
- u_int8_t me_max_tags;
- u_int8_t me_max_sys_drives;
- u_int8_t me_max_arms;
- u_int8_t me_max_spans;
- u_int8_t res2;
- u_int32_t res3;
- u_int32_t me_mem_size;
- u_int32_t me_cache_size;
- u_int32_t me_flash_size;
- u_int32_t me_nvram_size;
- u_int16_t me_mem_type;
- u_int16_t me_clock_speed;
- u_int16_t me_mem_speed;
- u_int16_t me_hardware_speed;
- u_int8_t res4[12];
- u_int16_t me_max_commands;
- u_int16_t me_max_sg;
- u_int16_t me_max_dp;
- u_int16_t me_max_iod;
- u_int16_t me_max_comb;
- u_int8_t me_latency;
- u_int8_t res5;
- u_int8_t me_scsi_timeout;
- u_int8_t res6;
- u_int16_t me_min_freelines;
- u_int8_t res7[8];
- u_int8_t me_rate_const;
- u_int8_t res8[11];
- u_int16_t me_physblk;
- u_int16_t me_logblk;
- u_int16_t me_maxblk;
- u_int16_t me_blocking_factor;
- u_int16_t me_cacheline;
- u_int8_t me_scsi_cap;
- u_int8_t res9[5];
- u_int16_t me_firmware_build;
- u_int8_t me_fault_mgmt_type;
- u_int8_t res10;
- u_int32_t me_firmware_features;
- u_int8_t res11[8];
-} __attribute__ ((packed));
-
-struct mlx_enq_sys_drive /* MLX_CMD_ENQSYSDRIVE returns an array of 32 of these */
-{
- u_int32_t sd_size;
- u_int8_t sd_state;
- u_int8_t sd_raidlevel;
- u_int16_t res1;
-} __attribute__ ((packed));
-
-struct mlx_eventlog_entry /* MLX_CMD_LOGOP/MLX_LOGOP_GET */
-{
- u_int8_t el_type;
- u_int8_t el_length;
- u_char el_target:5;
- u_char el_channel:3;
- u_char el_lun:6;
- u_char res1:2;
- u_int16_t el_seqno;
- u_char el_errorcode:7;
- u_char el_valid:1;
- u_int8_t el_segment;
- u_char el_sensekey:4;
- u_char res2:1;
- u_char el_ILI:1;
- u_char el_EOM:1;
- u_char el_filemark:1;
- u_int8_t el_information[4];
- u_int8_t el_addsense;
- u_int8_t el_csi[4];
- u_int8_t el_asc;
- u_int8_t el_asq;
- u_int8_t res3[12];
-} __attribute__ ((packed));
-
-#define MLX_LOGOP_GET 0x00 /* operation codes for MLX_CMD_LOGOP */
-#define MLX_LOGMSG_SENSE 0x00 /* log message contents codes */
-
-struct mlx_rebuild_stat /* MLX_CMD_REBUILDSTAT */
-{
- u_int32_t rb_drive;
- u_int32_t rb_size;
- u_int32_t rb_remaining;
-} __attribute__ ((packed));
-
-struct mlx_config2
-{
- u_int16_t cf_flags1;
-#define MLX_CF2_ACTV_NEG (1<<1)
-#define MLX_CF2_NORSTRTRY (1<<7)
-#define MLX_CF2_STRGWRK (1<<8)
-#define MLX_CF2_HPSUPP (1<<9)
-#define MLX_CF2_NODISCN (1<<10)
-#define MLX_CF2_ARM (1<<13)
-#define MLX_CF2_OFM (1<<15)
-#define MLX_CF2_AEMI (MLX_CF2_ARM | MLX_CF2_OFM)
- u_int8_t cf_oemid;
- u_int8_t cf_oem_model;
- u_int8_t cf_physical_sector;
- u_int8_t cf_logical_sector;
- u_int8_t cf_blockfactor;
- u_int8_t cf_flags2;
-#define MLX_CF2_READAH (1<<0)
-#define MLX_CF2_BIOSDLY (1<<1)
-#define MLX_CF2_REASS1S (1<<4)
-#define MLX_CF2_FUAENABL (1<<6)
-#define MLX_CF2_R5ALLS (1<<7)
- u_int8_t cf_rcrate;
- u_int8_t cf_res1;
- u_int8_t cf_blocks_per_cache_line;
- u_int8_t cf_blocks_per_stripe;
- u_int8_t cf_scsi_param_0;
- u_int8_t cf_scsi_param_1;
- u_int8_t cf_scsi_param_2;
- u_int8_t cf_scsi_param_3;
- u_int8_t cf_scsi_param_4;
- u_int8_t cf_scsi_param_5;
- u_int8_t cf_scsi_initiator_id;
- u_int8_t cf_res2;
- u_int8_t cf_startup_mode;
- u_int8_t cf_simultaneous_spinup_devices;
- u_int8_t cf_delay_between_spinups;
- u_int8_t cf_res3;
- u_int16_t cf_checksum;
-} __attribute__ ((packed));
-
-struct mlx_sys_drv_span
-{
- u_int32_t sp_start_lba;
- u_int32_t sp_nblks;
- u_int8_t sp_arm[8];
-} __attribute__ ((packed));
-
-struct mlx_sys_drv
-{
- u_int8_t sd_status;
- u_int8_t sd_ext_status;
- u_int8_t sd_mod1;
- u_int8_t sd_mod2;
- u_int8_t sd_raidlevel;
-#define MLX_SYS_DRV_WRITEBACK (1<<7)
-#define MLX_SYS_DRV_RAID0 0
-#define MLX_SYS_DRV_RAID1 1
-#define MLX_SYS_DRV_RAID3 3
-#define MLX_SYS_DRV_RAID5 5
-#define MLX_SYS_DRV_RAID6 6
-#define MLX_SYS_DRV_JBOD 7
- u_int8_t sd_valid_arms;
- u_int8_t sd_valid_spans;
- u_int8_t sd_init_state;
-#define MLX_SYS_DRV_INITTED 0x81;
- struct mlx_sys_drv_span sd_span[4];
-} __attribute__ ((packed));
-
-struct mlx_phys_drv
-{
- u_int8_t pd_flags1;
-#define MLX_PHYS_DRV_PRESENT (1<<0)
- u_int8_t pd_flags2;
-#define MLX_PHYS_DRV_OTHER 0x00
-#define MLX_PHYS_DRV_DISK 0x01
-#define MLX_PHYS_DRV_SEQUENTIAL 0x02
-#define MLX_PHYS_DRV_CDROM 0x03
-#define MLX_PHYS_DRV_FAST20 (1<<3)
-#define MLX_PHYS_DRV_SYNC (1<<4)
-#define MLX_PHYS_DRV_FAST (1<<5)
-#define MLX_PHYS_DRV_WIDE (1<<6)
-#define MLX_PHYS_DRV_TAG (1<<7)
- u_int8_t pd_status;
-#define MLX_PHYS_DRV_DEAD 0x00
-#define MLX_PHYS_DRV_WRONLY 0x02
-#define MLX_PHYS_DRV_ONLINE 0x03
-#define MLX_PHYS_DRV_STANDBY 0x10
- u_int8_t pd_res1;
- u_int8_t pd_period;
- u_int8_t pd_offset;
- u_int32_t pd_config_size;
-} __attribute__ ((packed));
-
-struct mlx_core_cfg
-{
- u_int8_t cc_num_sys_drives;
- u_int8_t cc_res1[3];
- struct mlx_sys_drv cc_sys_drives[32];
- struct mlx_phys_drv cc_phys_drives[5 * 16];
-} __attribute__ ((packed));
-
-struct mlx_dcdb
-{
- u_int8_t dcdb_target:4;
- u_int8_t dcdb_channel:4;
- u_int8_t dcdb_flags;
-#define MLX_DCDB_NO_DATA 0x00
-#define MLX_DCDB_DATA_IN 0x01
-#define MLX_DCDB_DATA_OUT 0x02
-#define MLX_DCDB_EARLY_STATUS (1<<2)
-#define MLX_DCDB_TIMEOUT_10S 0x10
-#define MLX_DCDB_TIMEOUT_60S 0x20
-#define MLX_DCDB_TIMEOUT_20M 0x30
-#define MLX_DCDB_TIMEOUT_24H 0x40
-#define MLX_DCDB_NO_AUTO_SENSE (1<<6)
-#define MLX_DCDB_DISCONNECT (1<<7)
- u_int16_t dcdb_datasize;
- u_int32_t dcdb_physaddr;
- u_int8_t dcdb_cdb_length:4;
- u_int8_t dcdb_datasize_high:4;
- u_int8_t dcdb_sense_length;
- u_int8_t dcdb_cdb[12];
- u_int8_t dcdb_sense[64];
- u_int8_t dcdb_status;
- u_int8_t res1;
-} __attribute__ ((packed));
-
-struct mlx_bbtable_entry
-{
- u_int32_t bbt_block_number;
- u_int8_t bbt_extent;
- u_int8_t res1;
- u_int8_t bbt_entry_type;
- u_int8_t bbt_system_drive:5;
- u_int8_t res2:3;
-} __attribute__ ((packed));
-
-#ifdef _KERNEL
-/*
* Inlines to build various command structures
*/
static __inline void
@@ -616,5 +285,3 @@
mc->mc_mailbox[0xb] = (f4 >> 24) & 0xff;
mc->mc_mailbox[0xc] = f5;
}
-
-#endif /* _KERNEL */
Index: usr.sbin/mlxcontrol/command.c
===================================================================
RCS file: /home/ncvs/src/usr.sbin/mlxcontrol/command.c,v
retrieving revision 1.2
diff -u -r1.2 command.c
--- usr.sbin/mlxcontrol/command.c 2000/04/11 23:04:17 1.2
+++ usr.sbin/mlxcontrol/command.c 2001/05/24 09:36:30
@@ -35,7 +35,6 @@
#include <err.h>
#include <dev/mlx/mlxio.h>
-#include <dev/mlx/mlxreg.h>
#include "mlxcontrol.h"
Index: usr.sbin/mlxcontrol/config.c
===================================================================
RCS file: /home/ncvs/src/usr.sbin/mlxcontrol/config.c,v
retrieving revision 1.2
diff -u -r1.2 config.c
--- usr.sbin/mlxcontrol/config.c 2000/04/11 23:04:17 1.2
+++ usr.sbin/mlxcontrol/config.c 2001/05/24 09:36:33
@@ -35,7 +35,6 @@
#include <err.h>
#include <dev/mlx/mlxio.h>
-#include <dev/mlx/mlxreg.h>
#include "mlxcontrol.h"
Index: usr.sbin/mlxcontrol/interface.c
===================================================================
RCS file: /home/ncvs/src/usr.sbin/mlxcontrol/interface.c,v
retrieving revision 1.2
diff -u -r1.2 interface.c
--- usr.sbin/mlxcontrol/interface.c 2000/04/11 23:04:17 1.2
+++ usr.sbin/mlxcontrol/interface.c 2001/05/24 09:36:33
@@ -34,7 +34,6 @@
#include <cam/scsi/scsi_all.h>
#include <dev/mlx/mlxio.h>
-#include <dev/mlx/mlxreg.h>
#include "mlxcontrol.h"
Index: usr.sbin/mlxcontrol/util.c
===================================================================
RCS file: /home/ncvs/src/usr.sbin/mlxcontrol/util.c,v
retrieving revision 1.2
diff -u -r1.2 util.c
--- usr.sbin/mlxcontrol/util.c 2000/04/11 23:04:17 1.2
+++ usr.sbin/mlxcontrol/util.c 2001/05/24 09:36:33
@@ -32,7 +32,6 @@
#include <string.h>
#include <dev/mlx/mlxio.h>
-#include <dev/mlx/mlxreg.h>
#include "mlxcontrol.h"
--+HP7ph2BbKc20aGI--
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