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Date:      Fri, 15 Nov 2013 07:10:42 +0000 (UTC)
From:      Konstantin Belousov <kib@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org
Subject:   svn commit: r258159 - in stable/10/sys: amd64/amd64 i386/i386 x86/include
Message-ID:  <201311150710.rAF7AgX1093583@svn.freebsd.org>

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Author: kib
Date: Fri Nov 15 07:10:42 2013
New Revision: 258159
URL: http://svnweb.freebsd.org/changeset/base/258159

Log:
  MFC r257856:
  Add bits for the AMD features from CPUID function 0x80000001 ECX,
  described in the rev. 3.0 of the Kabini BKDG, document 48751.pdf.
  
  Approved by:	re (gjb)

Modified:
  stable/10/sys/amd64/amd64/identcpu.c
  stable/10/sys/i386/i386/identcpu.c
  stable/10/sys/x86/include/specialreg.h
Directory Properties:
  stable/10/sys/   (props changed)

Modified: stable/10/sys/amd64/amd64/identcpu.c
==============================================================================
--- stable/10/sys/amd64/amd64/identcpu.c	Fri Nov 15 07:09:24 2013	(r258158)
+++ stable/10/sys/amd64/amd64/identcpu.c	Fri Nov 15 07:10:42 2013	(r258159)
@@ -366,18 +366,18 @@ printcpuinfo(void)
 				"\017<b14>"
 				"\020LWP"	/* Lightweight Profiling */
 				"\021FMA4"	/* 4-operand FMA instructions */
-				"\022<b17>"
+				"\022TCE"	/* Translation Cache Extension */
 				"\023<b18>"
 				"\024NodeId"	/* NodeId MSR support */
 				"\025<b20>"
 				"\026TBM"	/* Trailing Bit Manipulation */
 				"\027Topology"	/* Topology Extensions */
-				"\030<b23>"
-				"\031<b24>"
+				"\030PCXC"	/* Core perf count */
+				"\031PNXC"	/* NB perf count */
 				"\032<b25>"
-				"\033<b26>"
-				"\034<b27>"
-				"\035<b28>"
+				"\033DBE"	/* Data Breakpoint extension */
+				"\034PTSC"	/* Performance TSC */
+				"\035PL2I"	/* L2I perf count */
 				"\036<b29>"
 				"\037<b30>"
 				"\040<b31>"

Modified: stable/10/sys/i386/i386/identcpu.c
==============================================================================
--- stable/10/sys/i386/i386/identcpu.c	Fri Nov 15 07:09:24 2013	(r258158)
+++ stable/10/sys/i386/i386/identcpu.c	Fri Nov 15 07:10:42 2013	(r258159)
@@ -842,18 +842,18 @@ printcpuinfo(void)
 				"\017<b14>"
 				"\020LWP"	/* Lightweight Profiling */
 				"\021FMA4"	/* 4-operand FMA instructions */
-				"\022<b17>"
+				"\022TCE"	/* Translation Cache Extension */
 				"\023<b18>"
 				"\024NodeId"	/* NodeId MSR support */
 				"\025<b20>"
 				"\026TBM"	/* Trailing Bit Manipulation */
 				"\027Topology"	/* Topology Extensions */
-				"\030<b23>"
-				"\031<b24>"
+				"\030PCXC"	/* Core perf count */
+				"\031PNXC"	/* NB perf count */
 				"\032<b25>"
-				"\033<b26>"
-				"\034<b27>"
-				"\035<b28>"
+				"\033DBE"	/* Data Breakpoint extension */
+				"\034PTSC"	/* Performance TSC */
+				"\035PL2I"	/* L2I perf count */
 				"\036<b29>"
 				"\037<b30>"
 				"\040<b31>"

Modified: stable/10/sys/x86/include/specialreg.h
==============================================================================
--- stable/10/sys/x86/include/specialreg.h	Fri Nov 15 07:09:24 2013	(r258158)
+++ stable/10/sys/x86/include/specialreg.h	Fri Nov 15 07:10:42 2013	(r258159)
@@ -201,9 +201,15 @@
 #define	AMDID2_WDT	0x00002000
 #define	AMDID2_LWP	0x00008000
 #define	AMDID2_FMA4	0x00010000
+#define	AMDID2_TCE	0x00020000
 #define	AMDID2_NODE_ID	0x00080000
 #define	AMDID2_TBM	0x00200000
 #define	AMDID2_TOPOLOGY	0x00400000
+#define	AMDID2_PCXC	0x00800000
+#define	AMDID2_PNXC	0x01000000
+#define	AMDID2_DBE	0x04000000
+#define	AMDID2_PTSC	0x08000000
+#define	AMDID2_PTSCEL2I	0x10000000
 
 /*
  * CPUID instruction 1 eax info



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