From owner-svn-src-all@FreeBSD.ORG Fri Sep 14 09:38:55 2012 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 16EA61065670; Fri, 14 Sep 2012 09:38:55 +0000 (UTC) (envelope-from gber@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id EC42C8FC17; Fri, 14 Sep 2012 09:38:54 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id q8E9csM6089501; Fri, 14 Sep 2012 09:38:54 GMT (envelope-from gber@svn.freebsd.org) Received: (from gber@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id q8E9csJB089497; Fri, 14 Sep 2012 09:38:54 GMT (envelope-from gber@svn.freebsd.org) Message-Id: <201209140938.q8E9csJB089497@svn.freebsd.org> From: Grzegorz Bernacki Date: Fri, 14 Sep 2012 09:38:54 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r240486 - in head/sys/arm: arm include X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 14 Sep 2012 09:38:55 -0000 Author: gber Date: Fri Sep 14 09:38:54 2012 New Revision: 240486 URL: http://svn.freebsd.org/changeset/base/240486 Log: Support identification of new PJ4B cores. Obtained from: Semihalf Modified: head/sys/arm/arm/cpufunc.c head/sys/arm/arm/identcpu.c head/sys/arm/include/armreg.h Modified: head/sys/arm/arm/cpufunc.c ============================================================================== --- head/sys/arm/arm/cpufunc.c Fri Sep 14 09:36:35 2012 (r240485) +++ head/sys/arm/arm/cpufunc.c Fri Sep 14 09:38:54 2012 (r240486) @@ -1415,6 +1415,7 @@ set_cpufuncs() #if defined(CPU_MV_PJ4B) if (cputype == CPU_ID_MV88SV581X_V6 || cputype == CPU_ID_MV88SV581X_V7 || + cputype == CPU_ID_MV88SV584X_V7 || cputype == CPU_ID_ARM_88SV581X_V6 || cputype == CPU_ID_ARM_88SV581X_V7) { if (cpu_pfr(0) & ARM_PFR0_THUMBEE_MASK) @@ -1425,8 +1426,8 @@ set_cpufuncs() get_cachetype_cp15(); pmap_pte_init_mmu_v6(); goto out; - } else if (cputype == CPU_ID_ARM_88SV584X || - cputype == CPU_ID_MV88SV584X) { + } else if (cputype == CPU_ID_ARM_88SV584X_V6 || + cputype == CPU_ID_MV88SV584X_V6) { cpufuncs = pj4bv6_cpufuncs; get_cachetype_cp15(); pmap_pte_init_mmu_v6(); Modified: head/sys/arm/arm/identcpu.c ============================================================================== --- head/sys/arm/arm/identcpu.c Fri Sep 14 09:36:35 2012 (r240485) +++ head/sys/arm/arm/identcpu.c Fri Sep 14 09:38:54 2012 (r240486) @@ -321,9 +321,11 @@ const struct cpuidtab cpuids[] = { generic_steppings }, { CPU_ID_ARM_88SV581X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV581x", generic_steppings }, - { CPU_ID_MV88SV584X, CPU_CLASS_MARVELL, "Sheeva 88SV584x", + { CPU_ID_MV88SV584X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV584x", generic_steppings }, - { CPU_ID_ARM_88SV584X, CPU_CLASS_MARVELL, "Sheeva 88SV584x", + { CPU_ID_ARM_88SV584X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV584x", + generic_steppings }, + { CPU_ID_MV88SV584X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV584x", generic_steppings }, { 0, CPU_CLASS_NONE, NULL, NULL } Modified: head/sys/arm/include/armreg.h ============================================================================== --- head/sys/arm/include/armreg.h Fri Sep 14 09:36:35 2012 (r240485) +++ head/sys/arm/include/armreg.h Fri Sep 14 09:38:54 2012 (r240486) @@ -170,11 +170,12 @@ #define CPU_ID_MV88SV581X_V6 0x560F5810 /* Marvell Sheeva 88SV581x v6 Core */ #define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */ -#define CPU_ID_MV88SV584X 0x561F5840 /* Marvell Sheeva 88SV584x v6 Core */ +#define CPU_ID_MV88SV584X_V6 0x561F5840 /* Marvell Sheeva 88SV584x v6 Core */ +#define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */ /* Marvell's CPUIDs with ARM ID in implementor field */ #define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */ #define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */ -#define CPU_ID_ARM_88SV584X 0x410FB024 /* Marvell Sheeva 88SV584x v6 Core */ +#define CPU_ID_ARM_88SV584X_V6 0x410FB020 /* Marvell Sheeva 88SV584x v6 Core */ #define CPU_ID_FA526 0x66015260 #define CPU_ID_FA626TE 0x66056260