From owner-freebsd-arm@FreeBSD.ORG Thu Sep 12 10:49:00 2013 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id B0BDF4C2 for ; Thu, 12 Sep 2013 10:49:00 +0000 (UTC) (envelope-from onwahe@gmail.com) Received: from mail-qe0-x233.google.com (mail-qe0-x233.google.com [IPv6:2607:f8b0:400d:c02::233]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 733EA280E for ; Thu, 12 Sep 2013 10:49:00 +0000 (UTC) Received: by mail-qe0-f51.google.com with SMTP id ne12so6420807qeb.38 for ; Thu, 12 Sep 2013 03:48:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=7e17aUiIDIbs7Jnk70ibLrua7F8Bw+Scf6qJJgmEo7U=; b=Z2dhwxMmBIf08xgQVLKLmFVC2nTjvq8PTDmt83AVxcqmTXFBZ6sZoBC70Tdf5n7KYZ 7BVTmWDql9Ds+DrNCgDhJLXkbd37o8ukpfe0igKd5nyXbaIHPlsefFDVQIJoZwtuPR8G Y6KiACAm6XU7/BWHVbElekzUxNX2LVNJUKAWT7IOlOrMEfEzrc2ROgsG/NLDpEd2d8w6 T+1c2DyFuqF3vaQkz5yDewhBnM1M/Ab9RMY31JTMQa117CrmY/CmMjFYlFivhAAfG2SM zt4KTp+0O1vCs6s00RCoHmH324SQsMQvr7CWX37NeulgvX36Fys4EzszRwHWGFkaoCbx Is0w== MIME-Version: 1.0 X-Received: by 10.229.79.70 with SMTP id o6mr12446064qck.21.1378982939417; Thu, 12 Sep 2013 03:48:59 -0700 (PDT) Received: by 10.140.90.7 with HTTP; Thu, 12 Sep 2013 03:48:59 -0700 (PDT) In-Reply-To: <20130910154335.GT68682@funkthat.com> References: <20130910154335.GT68682@funkthat.com> Date: Thu, 12 Sep 2013 12:48:59 +0200 Message-ID: Subject: Re: Architecture vs. bus vs. device DMA cache coherency From: Svatopluk Kraus To: John-Mark Gurney Content-Type: text/plain; charset=ISO-8859-1 X-Content-Filtered-By: Mailman/MimeDel 2.1.14 Cc: freebsd-arm@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Sep 2013 10:49:00 -0000 On Tue, Sep 10, 2013 at 5:43 PM, John-Mark Gurney wrote: > Svatopluk Kraus wrote this message on Tue, Sep 10, 2013 at 13:19 +0200: > > Even in DMA cache coherent architectures there could be not-coherent DMA > > busses and/or devices. Thus, each bus and/or device should be described > by > > its bus_dma_tag and the tag should carry information about DMA cache > > coherency. > > I've thought about this a lot myself, and I'm not familar w/ a bus (that > isn't main memory) or device that isn't cache coherent... Most busses > write to memory through an arbiter (north bridge or cpu/soc) that does > the proper read/modify/write cycles to get the memory there. I have > not heard of another bus/device that does their own read/modify/write > cycles to get their writes to memory. Can you name a current bus/device > that does this? > > Our busdma system does have issues that if you try to dma to say, > video memory, we don't handle that (well) because we assume that all > memory is a flat space and belongs to nexus, but this isn't always > correct. > > If you have an architecture like this, can you please tell use which > system you are trying to fix? Well, bus DMA implementation is MD code. We have taken into account ARM architecture mainly and tried to cover not-coherent ARMs, ARMs with ACP, and coherent ARMs. However, bus_dma_tag_t is common interface, so we've spread our thoughts and added to our model even hypotetical cases. You are right that devices with own memory on them, which is not accessed thru a bus from device side, are an issue. Like fast data (video) grabbers with dual-ported RAMs. Svatopluk Kraus