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Date: Thu, 24 Jul 1997 17:09:02 -0600
From: vanmaren@fast.cs.utah.edu (Kevin Van Maren)
Message-Id: <199707242309.RAA14938@fast.cs.utah.edu>
To: lamaster@george.arc.nasa.gov, terry@lambert.org
Subject: Re: Lots 'o PCI slots
Cc: freebsd-smp@FreeBSD.ORG
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> It would be a relatively cheap method of obtaining background
> distributed cache coherency processing (among other things).  One
> might even use the i960 for the scheduler and for forcible process
> migration.

Actually, the PCI cache-coherence isn't exactly `normal'.  Also,
as I mentioned, it is broken with PCI 2.1 bridges as well as with
the i960 I2O controller.

Kevin