From owner-freebsd-hackers@FreeBSD.ORG Tue Aug 31 08:15:27 2010 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 712EB106564A; Tue, 31 Aug 2010 08:15:27 +0000 (UTC) (envelope-from mavbsd@gmail.com) Received: from mail-fx0-f54.google.com (mail-fx0-f54.google.com [209.85.161.54]) by mx1.freebsd.org (Postfix) with ESMTP id CA1028FC0A; Tue, 31 Aug 2010 08:15:26 +0000 (UTC) Received: by fxm4 with SMTP id 4so4386345fxm.13 for ; Tue, 31 Aug 2010 01:15:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:message-id:date:from :user-agent:mime-version:to:cc:subject:references:in-reply-to :x-enigmail-version:content-type:content-transfer-encoding; bh=fNWjM43awMWNj/+ZLF/WYK3XLUos+0gEgMiJZWp9DD4=; b=PaEI6kA7WZ/WuH8MnBHcKD/78zcICocMRERnmj71xHLsl40GNSTFQtXASKwy1LWGAR bYIKUypFWLKlG6mCqkeU290ab6YKX5NxHTORguFTi7o7UqsDE3J9KxzBHoOiI7+Z2Oqu AA4o8t9q/kPcHmJQNEpuqGEa0acg9AQMeZ34I= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:x-enigmail-version:content-type :content-transfer-encoding; b=dj0nZY5IdSBLKWfF/cBxVtIm6QAgsX13JxDq7GXuIfzw0iEIvVrrhR3thC5XtsPGh5 XqY2ox6EnHoGDppnrCEf7dlsD7IQ3xYkVWaWrQCtFhU1XzGtpHjc3zxpU7Raq1sYxQFZ TwqZ1+C0+4lS3p/EDZIQrxvtMaLrxBSQA/apQ= Received: by 10.223.119.137 with SMTP id z9mr2647403faq.87.1283242525639; Tue, 31 Aug 2010 01:15:25 -0700 (PDT) Received: from mavbook2.mavhome.dp.ua (pc.mavhome.dp.ua [212.86.226.226]) by mx.google.com with ESMTPS id p2sm3828140fak.22.2010.08.31.01.15.24 (version=SSLv3 cipher=RC4-MD5); Tue, 31 Aug 2010 01:15:25 -0700 (PDT) Sender: Alexander Motin Message-ID: <4C7CBA15.8010009@FreeBSD.org> Date: Tue, 31 Aug 2010 11:15:17 +0300 From: Alexander Motin User-Agent: Thunderbird 2.0.0.23 (X11/20091212) MIME-Version: 1.0 To: "YAMAMOTO, Taku" References: <4C7A5C28.1090904@FreeBSD.org> <20100830110932.23425932@ernst.jennejohn.org> <4C7B82EA.2040104@FreeBSD.org> <20100830195941.9731109c.taku@tackymt.homeip.net> <4C7B91EC.5070906@FreeBSD.org> In-Reply-To: <4C7B91EC.5070906@FreeBSD.org> X-Enigmail-Version: 0.96.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Cc: freebsd-hackers@freebsd.org, FreeBSD-Current Subject: Re: One-shot-oriented event timers management X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Aug 2010 08:15:27 -0000 Alexander Motin wrote: > YAMAMOTO, Taku wrote: >> On Mon, 30 Aug 2010 13:07:38 +0300 >> Alexander Motin wrote: >>> Gary Jennejohn wrote: >> (snip) >>>> So, what else did you do to reduce interrupts so much? >>>> >>>> Ah, I think I see it now. My desktop has only C1 enabled. Is that it? >>>> Unfortunately, it appears that only C1 is supported :( >>> Yes, as I have said, at this moment empty ticks skipped only while CPU >>> is in C2/C3 states. In C1 state there is no way to handle lost events on >>> wake up. While it may be not very dangerous, it is not very good. >> There's an alternative way to catch exit-from-C1 atomically: >> use MWAIT with bit0 of ECX set (``Treat masked interrupts as break events'' >> in Intel 64 and IA-32 Architecthres Software Developer's Manual). >> >> In this way we can put each core individually into deeper Cx state without >> additional costs (SMIs and the like) as a bonus. >> >> The problem is that it may be unavailable to earlier CPUs that support >> MONITOR/MWAIT instructions: >> we should check the presense of this feature by examining bit0 and bit1 of ECX >> that is returned by CPUID 5. > > Thank you for the hint. I will investigate it now. But it still help > only x86 systems. I have no idea how power management works on > arm/mips/ppc/..., but I assume that periodic wake up there also may be > not free. I have looked on these MWAIT features. They indeed allow to wake up with interrupts disabled, but I am worrying about the C-state in which CPU goes in that case. MWAIT states are CPU C-STATES, not ACPI C-states. So I have doubts that using MWAIT instead of HLT on ACPI system is correct. Also I have found some comments that MWAIT on AMD 10h family CPUs does not allows CPU to go to C1E state, while HLT does. So it is not a complete (worse) equivalent. Later AMD CPUs just do not support MWAIT. -- Alexander Motin