Date: Wed, 22 Feb 2012 16:31:30 -0500 From: John Baldwin <jhb@freebsd.org> To: JD Louw <jdl.ntq@gmail.com> Cc: freebsd-drivers@freebsd.org Subject: Re: bus_dma coalesce advice Message-ID: <201202221631.30508.jhb@freebsd.org> In-Reply-To: <CAB-7mS4Q3Z%2Bc8H8rJV6z17vmMab2djTO23s2Z8Z3HSyGKFyuUQ@mail.gmail.com> References: <CAB-7mS5JXO8khFLWnSPhu9nadTW9JWakCp-3bP4vwoJ5KXsX8w@mail.gmail.com> <201202211504.34169.jhb@freebsd.org> <CAB-7mS4Q3Z%2Bc8H8rJV6z17vmMab2djTO23s2Z8Z3HSyGKFyuUQ@mail.gmail.com>
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On Wednesday, February 22, 2012 10:06:23 am JD Louw wrote:
> On Tue, Feb 21, 2012 at 10:04 PM, John Baldwin <jhb@freebsd.org> wrote:
> > On Monday, February 20, 2012 1:05:40 pm JD Louw wrote:
> >> Hi,
> >>
> >> I have a Xilinx FPGA PCIe DMA design that I'd like to get going on
> >> FreeBSD. I'd like some advice on the best practice of the bus_dma
> >> functions. Specifically, I'd like to understand how best to coalesce
> >> multiple DMA transactions.
> >>
> >> Using the bus_dma_tag_create and bus_dmamem_alloc functions I create
> >> 256 contiguous descriptors.
> >>
> >> bus_dma_tag_create(NULL, /* parent */
> >> 4, /* alignment */
> >> 0, /* bounds */
> >> BUS_SPACE_MAXADDR, /* lowaddr */
> >> BUS_SPACE_MAXADDR, /* highaddr */
> >> NULL, NULL, /* filter, filterarg */
> >> 256*sizeof(descriptor), /* maxsize */
> >> 1, /* nsegments */
> >> 256*sizeof(descriptor), /* maxsegsize */
> >> BUS_DMA_ALLOCNOW, /* flags */
> >> NULL, NULL, /* lockfunc, lockarg */
> >> &desc_tag); /* dmat */
> >>
> >> I then create another bus_dma_tag for the data:
> >>
> >> bus_dma_tag_create(NULL, /* parent */
> >> 4, /* alignment */
> >> 0, /* bounds */
> >> BUS_SPACE_MAXADDR, /* lowaddr */
> >> BUS_SPACE_MAXADDR, /* highaddr */
> >> NULL, NULL, /* filter, filterarg */
> >> 0xFFFFF, /* maxsize - 1MB */
> >> 256, /* nsegments */
> >> 0x1000, /* maxsegsize - 4KB*/
> >> BUS_DMA_ALLOCNOW, /* flags */
> >> NULL, NULL, /* lockfunc, lockarg */
> >> &data_tag); /* dmat */
> >>
> >> Now my question: In order to batch several mbufs/uios in into the 256
> >> descriptors I'd like to do multiple bus_dmamap_loads on the data tag.
> >> But reading the bus_dmamap_load_mbuf/uio code it looks like this is
> >> not a good idea. Each mapping operation does not subtract its nsegment
> >> count from the tag maximum nsegment count, so at some point
> >> bus_dmamap_load will overrun my 256 descriptors.
> >
> > Does your DMA engine really allow a single transaction to span more tha=
n 256
> > descriptors? (The 'nsegmenets' is the maximum number of S/G entries fo=
r a
> > single transaction, not the number of entries in your ring.)
> >
> >> Do I need to allocate a separate set of descriptors for each bus_dmama=
pping?
> >>
> >> Any advice much appreciated,
> >
> > Typically in a NIC driver you will use bus_dmamap_load_mbuf_sg() to pop=
ulate
> > an array of S/G elements on the stack. You can check the returned valu=
e for
> > the number of segments and handle the case where it exceeds the number =
of
> > segments you actually have available (e.g. by calling m_collapse() or
> > m_defrag() or just queueing the packet until you get a TX completion in=
terrupt
> > that frees up some descriptors). Note that for all of those cases you =
will
> > need to do a bus_dmamap_unload() first.
> >
> > --
> > John Baldwin
>=20
> I'm not sure how NIC ring buffer descriptors are structured, but the
> FPGA DMA descriptor structure looks as follows:
>=20
> struct descriptor {
> uint64_t seg_phys_addr;
> uint32_t seg_len;
> uint64_t next_desc_phys_addr;
> };
>=20
> The FPGA's descriptors are chained together in a linked list using
> physical addressing, so I can chain together as many descriptors as I
> want to. The chain is terminated by a NULL pointer. Something like
> this:
>=20
> d------>d------->d------>NULL
> | | |
> | | |
> =E2=8C=84 =E2=8C=84 =E2=8C=84
> seg seg seg
>=20
>=20
> The physical address of the first descriptor is written to a DMA
> address register and the engine is started by writing to the DMA
> control register. A hardware interrupt is generated once the DMA
> engine is done walking the descriptor chain and sucking in all
> segments.
>=20
>=20
> I'd like lessen the interrupt load by loading more than one uio/mbuf
> map into the chain before starting off the DMA. But since I don't know
> beforehand how many segments each uio/mbuf load will occupy I may
> overrun the 256 chain elements.
Yes, this is the same problem. Just keep loading packets on until
you either run out of mbufs, or you have an mbuf that has too many
segments. If the mbuf has too many segments, you put it back in the
IFQ so that it will be retried once you get an interrupt from your
card. Just keep track of your current pending global chain you are
building in your softc.
=2D-=20
John Baldwin
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