From owner-svn-src-all@freebsd.org Fri Nov 24 11:20:11 2017 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id C2ED1DE12A4; Fri, 24 Nov 2017 11:20:11 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 8C16370060; Fri, 24 Nov 2017 11:20:11 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id vAOBKAg1068837; Fri, 24 Nov 2017 11:20:10 GMT (envelope-from avg@FreeBSD.org) Received: (from avg@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id vAOBKAOS068836; Fri, 24 Nov 2017 11:20:10 GMT (envelope-from avg@FreeBSD.org) Message-Id: <201711241120.vAOBKAOS068836@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: avg set sender to avg@FreeBSD.org using -f From: Andriy Gapon Date: Fri, 24 Nov 2017 11:20:10 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r326152 - head/sys/amd64/vmm/amd X-SVN-Group: head X-SVN-Commit-Author: avg X-SVN-Commit-Paths: head/sys/amd64/vmm/amd X-SVN-Commit-Revision: 326152 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 24 Nov 2017 11:20:11 -0000 Author: avg Date: Fri Nov 24 11:20:10 2017 New Revision: 326152 URL: https://svnweb.freebsd.org/changeset/base/326152 Log: amd-vi: fix and extend definition of Command and Event Status Register (0x2020) The defined bits are the lower bits, not the higher ones. Also, the specification has been extended to define bits 0:18 and they all could potentially be interesting to us, so extend the width of the field accordingly. Reviewed by: anish Modified: head/sys/amd64/vmm/amd/amdvi_priv.h Modified: head/sys/amd64/vmm/amd/amdvi_priv.h ============================================================================== --- head/sys/amd64/vmm/amd/amdvi_priv.h Fri Nov 24 11:10:36 2017 (r326151) +++ head/sys/amd64/vmm/amd/amdvi_priv.h Fri Nov 24 11:20:10 2017 (r326152) @@ -230,8 +230,8 @@ struct amdvi_ctrl { uint64_t :45; uint32_t evt_tail:19; uint64_t :45; - uint64_t :56; - uint8_t status:8; + uint8_t status:19; + uint64_t :45; uint64_t pad2; uint8_t :4; uint16_t ppr_head:15;