From owner-svn-src-head@freebsd.org Sat Nov 19 16:36:39 2016 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 9620BC4AD00; Sat, 19 Nov 2016 16:36:39 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 4B35EB8B; Sat, 19 Nov 2016 16:36:39 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id uAJGacRr051116; Sat, 19 Nov 2016 16:36:38 GMT (envelope-from br@FreeBSD.org) Received: (from br@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id uAJGackw051113; Sat, 19 Nov 2016 16:36:38 GMT (envelope-from br@FreeBSD.org) Message-Id: <201611191636.uAJGackw051113@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: br set sender to br@FreeBSD.org using -f From: Ruslan Bukin Date: Sat, 19 Nov 2016 16:36:38 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r308845 - in head/sys/mips: include mips X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 19 Nov 2016 16:36:39 -0000 Author: br Date: Sat Nov 19 16:36:38 2016 New Revision: 308845 URL: https://svnweb.freebsd.org/changeset/base/308845 Log: Account for bigger secondary data cache line size. Secondary data cache line size can be bigger than primary data cache line size, so use biggest value as a minimum alignment. Submitted by: kan Sponsored by: DARPA, AFRL Modified: head/sys/mips/include/cache.h head/sys/mips/mips/busdma_machdep.c head/sys/mips/mips/cache_mipsNN.c Modified: head/sys/mips/include/cache.h ============================================================================== --- head/sys/mips/include/cache.h Sat Nov 19 16:23:54 2016 (r308844) +++ head/sys/mips/include/cache.h Sat Nov 19 16:36:38 2016 (r308845) @@ -161,6 +161,8 @@ extern struct mips_cache_ops mips_cache_ /* PRIMARY CACHE VARIABLES */ extern int mips_picache_linesize; extern int mips_pdcache_linesize; +extern int mips_sdcache_linesize; +extern int mips_dcache_max_linesize; #define __mco_noargs(prefix, x) \ do { \ Modified: head/sys/mips/mips/busdma_machdep.c ============================================================================== --- head/sys/mips/mips/busdma_machdep.c Sat Nov 19 16:23:54 2016 (r308844) +++ head/sys/mips/mips/busdma_machdep.c Sat Nov 19 16:36:38 2016 (r308845) @@ -226,7 +226,7 @@ busdma_init(void *dummy) /* Create a cache of buffers in standard (cacheable) memory. */ standard_allocator = busdma_bufalloc_create("buffer", - mips_pdcache_linesize, /* minimum_alignment */ + mips_dcache_max_linesize, /* minimum_alignment */ NULL, /* uma_alloc func */ NULL, /* uma_free func */ 0); /* uma_zcreate_flags */ @@ -236,7 +236,7 @@ busdma_init(void *dummy) * BUS_DMA_COHERENT flag. */ coherent_allocator = busdma_bufalloc_create("coherent", - mips_pdcache_linesize, /* minimum_alignment */ + mips_dcache_max_linesize, /* minimum_alignment */ busdma_bufalloc_alloc_uncacheable, busdma_bufalloc_free_uncacheable, 0); /* uma_zcreate_flags */ @@ -1061,10 +1061,10 @@ _bus_dmamap_unload(bus_dma_tag_t dmat, b static void bus_dmamap_sync_buf(vm_offset_t buf, int len, bus_dmasync_op_t op, int aligned) { - char tmp_cl[mips_pdcache_linesize], tmp_clend[mips_pdcache_linesize]; + char tmp_cl[mips_dcache_max_linesize], tmp_clend[mips_dcache_max_linesize]; vm_offset_t buf_cl, buf_clend; vm_size_t size_cl, size_clend; - int cache_linesize_mask = mips_pdcache_linesize - 1; + int cache_linesize_mask = mips_dcache_max_linesize - 1; /* * dcache invalidation operates on cache line aligned addresses @@ -1091,7 +1091,7 @@ bus_dmamap_sync_buf(vm_offset_t buf, int buf_cl = buf & ~cache_linesize_mask; size_cl = buf & cache_linesize_mask; buf_clend = buf + len; - size_clend = (mips_pdcache_linesize - + size_clend = (mips_dcache_max_linesize - (buf_clend & cache_linesize_mask)) & cache_linesize_mask; } @@ -1123,7 +1123,7 @@ bus_dmamap_sync_buf(vm_offset_t buf, int if (size_cl) mips_dcache_wbinv_range(buf_cl, size_cl); if (size_clend && (size_cl == 0 || - buf_clend - buf_cl > mips_pdcache_linesize)) + buf_clend - buf_cl > mips_dcache_max_linesize)) mips_dcache_wbinv_range(buf_clend, size_clend); break; @@ -1156,7 +1156,7 @@ bus_dmamap_sync_buf(vm_offset_t buf, int if (size_cl) mips_dcache_wbinv_range(buf_cl, size_cl); if (size_clend && (size_cl == 0 || - buf_clend - buf_cl > mips_pdcache_linesize)) + buf_clend - buf_cl > mips_dcache_max_linesize)) mips_dcache_wbinv_range(buf_clend, size_clend); break; Modified: head/sys/mips/mips/cache_mipsNN.c ============================================================================== --- head/sys/mips/mips/cache_mipsNN.c Sat Nov 19 16:23:54 2016 (r308844) +++ head/sys/mips/mips/cache_mipsNN.c Sat Nov 19 16:36:38 2016 (r308845) @@ -97,6 +97,8 @@ xlp_sync(void) */ int mips_picache_linesize; int mips_pdcache_linesize; +int mips_sdcache_linesize; +int mips_dcache_max_linesize; static int picache_size; static int picache_stride; @@ -157,6 +159,10 @@ mipsNN_cache_init(struct mips_cpuinfo * sdcache_size = cpuinfo->l2.dc_size; sdcache_way_mask = cpuinfo->l2.dc_nways - 1; + mips_sdcache_linesize = cpuinfo->l2.dc_linesize; + mips_dcache_max_linesize = MAX(mips_pdcache_linesize, + mips_sdcache_linesize); + #define CACHE_DEBUG #ifdef CACHE_DEBUG printf("Cache info:\n"); @@ -166,6 +172,7 @@ mipsNN_cache_init(struct mips_cpuinfo * printf(" picache_loopcount = %d\n", picache_loopcount); printf(" pdcache_stride = %d\n", pdcache_stride); printf(" pdcache_loopcount = %d\n", pdcache_loopcount); + printf(" max line size = %d\n", mips_dcache_max_linesize); #endif }