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Date:      Thu, 19 Apr 2001 11:34:27 -0700
From:      "Charles Burns" <burnscharlesn@hotmail.com>
To:        jgowdy@home.com, vince@oahu.WURLDLINK.NET
Cc:        lplist@closedsrc.org, kris@obsecurity.org, mwlist@lanfear.com, freebsd@sysmach.com, questions@FreeBSD.ORG
Subject:   Re: the AMD factor in FreeBSD
Message-ID:  <F25dZqou2VythhOjcdE00006593@hotmail.com>

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> > > Note that the AMD and Intel chips aren't slower because of 
>incompetence.
> > > They need to remain backwards-compatible with the 8086 instruction set
>and
> > > some of its methods of doing things. The 8086 processor sucks. It's
> > > architecture and design suck. They were never meant for general 
>purpose
> > > computing--more for operating dishwashers and the like. The fact that
>they
> > > have advanced so far is a testament to the ingenuity of humanity--and 
>to
>the
> > > stubbornness.
> > > Blame IBM. ;-)
> >
> > Hehe...  I thought the AMD/Intel were both CISC while the PowerPC
> > is RISC created by IBM/Motorola/Apple.  I guess until the 486, the x86
> > architecture was no match for workstations.
>
>All Intel and AMD x86 cpus today are RISC processors.  They implement their
>own hidden custom RISC architecture internally.  The x86 CISC instructions
>are translated into fixed length RISC instructions before they are
>processed.


I missed the post that this is a reply to somehow. You know, oddly enough 
the classic Pentium had less instructions than the Motorola PowerPC 604, so, 
in the classic sense of the term the Pentium was more RISC (REDUCED 
INSTRUCTION SET Chip) than the PPC. ;-)

The whole RISC thing has kinda died down, really. In general, RISC takes 
more instructions to do the same thing but can do more instructions per 
clock than CISC (Complex Instruction Set Chip--a term coined to 
differentiate from RISC). It ends up pretty much evening out. There are 
better things that chip designers can do to improve speed, for example, the 
Alpha can kick the crap out of any Motorola "RISC" chip.

You are quite right though, modern x86 CPUs translate everything to RISC 
micro-ops befor processing them. This takes far more transistors than just 
processing native RISC cod though, which is one reason why the G4 has so few 
transistors compared to the P4/Athlon. Theoretically pure RISC chips are 
cheaper and can run at higher clockspeeds, but there are so many other 
factors effecting these things that the results haven't really solidified.
Perhaps we should all just dump our systems and go buy some 21364's (when 
they arrive) and get a super optimizing compiler for those. Seti@home would 
fly. :-)
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