From owner-svn-src-head@freebsd.org Sat Jun 6 02:40:53 2020 Return-Path: Delivered-To: svn-src-head@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id E67E933FF56; Sat, 6 Jun 2020 02:40:53 +0000 (UTC) (envelope-from jhibbits@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 49f3fY52rXz4Xtk; Sat, 6 Jun 2020 02:40:53 +0000 (UTC) (envelope-from jhibbits@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id A7AC01AD5F; Sat, 6 Jun 2020 02:40:53 +0000 (UTC) (envelope-from jhibbits@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 0562ertN096676; Sat, 6 Jun 2020 02:40:53 GMT (envelope-from jhibbits@FreeBSD.org) Received: (from jhibbits@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 0562eqHg096669; Sat, 6 Jun 2020 02:40:52 GMT (envelope-from jhibbits@FreeBSD.org) Message-Id: <202006060240.0562eqHg096669@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jhibbits set sender to jhibbits@FreeBSD.org using -f From: Justin Hibbits Date: Sat, 6 Jun 2020 02:40:52 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r361859 - in head/sys/powerpc: aim include powerpc X-SVN-Group: head X-SVN-Commit-Author: jhibbits X-SVN-Commit-Paths: in head/sys/powerpc: aim include powerpc X-SVN-Commit-Revision: 361859 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.33 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 06 Jun 2020 02:40:54 -0000 Author: jhibbits Date: Sat Jun 6 02:40:52 2020 New Revision: 361859 URL: https://svnweb.freebsd.org/changeset/base/361859 Log: powerpc: Add a (CPU/runtime features) flags set to pcpu struct Summary: The point of this addition is to cache CPU behavior 'features', to avoid having to recompute based on CPU, etc. The first such use case is to avoid the unnecessary manipulation of the SLBs (Segment Lookaside Buffers) when using the Radix pmap on POWER9. Since we already get the PCPU pointer wherever we swap the SLB entries, we can use a cached flag to check if it's necessary to perform the operation anyway, and skip it when not. Reviewed by: bdragon Differential Revision: https://reviews.freebsd.org/D24908 Modified: head/sys/powerpc/aim/mmu_radix.c head/sys/powerpc/aim/trap_subr64.S head/sys/powerpc/include/pcpu.h head/sys/powerpc/powerpc/db_interface.c head/sys/powerpc/powerpc/genassym.c head/sys/powerpc/powerpc/mp_machdep.c Modified: head/sys/powerpc/aim/mmu_radix.c ============================================================================== --- head/sys/powerpc/aim/mmu_radix.c Sat Jun 6 02:28:21 2020 (r361858) +++ head/sys/powerpc/aim/mmu_radix.c Sat Jun 6 02:40:52 2020 (r361859) @@ -2327,6 +2327,7 @@ mmu_radix_bootstrap(vm_offset_t start, vm_offset_t end printf("%s done\n", __func__); pmap_bootstrapped = 1; dmaplimit = roundup2(powerpc_ptob(Maxmem), L2_PAGE_SIZE); + PCPU_SET(flags, PCPU_GET(flags) | PC_FLAG_NOSRS); } static void Modified: head/sys/powerpc/aim/trap_subr64.S ============================================================================== --- head/sys/powerpc/aim/trap_subr64.S Sat Jun 6 02:28:21 2020 (r361858) +++ head/sys/powerpc/aim/trap_subr64.S Sat Jun 6 02:40:52 2020 (r361859) @@ -87,6 +87,9 @@ restore_usersrs: */ restore_kernsrs: GET_CPUINFO(%r28) + lwz %r29, PC_FLAGS(%r28) + mtcr %r29 + btlr 0 addi %r28,%r28,PC_KERNSLB ld %r29,16(%r28) /* One past USER_SLB_SLOT */ cmpdi %r29,0 @@ -270,9 +273,13 @@ restore_kernsrs: std %r29,(savearea+CPUSAVE_R29)(%r3); \ std %r30,(savearea+CPUSAVE_R30)(%r3); \ std %r31,(savearea+CPUSAVE_R31)(%r3); \ + lwz %r28,PC_FLAGS(%r3); \ + mtcr %r28; \ + bt 0, 0f; /* Check to skip restoring SRs. */ \ mflr %r27; /* preserve LR */ \ bl restore_usersrs; /* uses r28-r31 */ \ mtlr %r27; \ +0: \ ld %r31,(savearea+CPUSAVE_R31)(%r3); \ ld %r30,(savearea+CPUSAVE_R30)(%r3); \ ld %r29,(savearea+CPUSAVE_R29)(%r3); \ Modified: head/sys/powerpc/include/pcpu.h ============================================================================== --- head/sys/powerpc/include/pcpu.h Sat Jun 6 02:28:21 2020 (r361858) +++ head/sys/powerpc/include/pcpu.h Sat Jun 6 02:40:52 2020 (r361859) @@ -50,6 +50,7 @@ struct pvo_entry; int pc_bsp; \ volatile int pc_awake; \ uint32_t pc_ipimask; \ + uint32_t pc_flags; /* cpu feature flags */ \ register_t pc_tempsave[CPUSAVE_LEN]; \ register_t pc_disisave[CPUSAVE_LEN]; \ register_t pc_dbsave[CPUSAVE_LEN]; \ @@ -76,6 +77,9 @@ struct pvo_entry; #else #define PCPU_MD_AIM_FIELDS PCPU_MD_AIM32_FIELDS #endif + +/* CPU feature flags, can be used for cached flow control. */ +#define PC_FLAG_NOSRS 0x80000000 #define BOOKE_CRITSAVE_LEN (CPUSAVE_LEN + 2) #define BOOKE_TLB_MAXNEST 4 Modified: head/sys/powerpc/powerpc/db_interface.c ============================================================================== --- head/sys/powerpc/powerpc/db_interface.c Sat Jun 6 02:28:21 2020 (r361858) +++ head/sys/powerpc/powerpc/db_interface.c Sat Jun 6 02:40:52 2020 (r361859) @@ -91,4 +91,5 @@ db_show_mdpcpu(struct pcpu *pc) db_printf("PPC: hwref = %#zx\n", pc->pc_hwref); db_printf("PPC: ipimask = %#x\n", pc->pc_ipimask); + db_printf("PPC: flags = %#x\n", pc->pc_flags); } Modified: head/sys/powerpc/powerpc/genassym.c ============================================================================== --- head/sys/powerpc/powerpc/genassym.c Sat Jun 6 02:28:21 2020 (r361858) +++ head/sys/powerpc/powerpc/genassym.c Sat Jun 6 02:40:52 2020 (r361859) @@ -64,6 +64,7 @@ ASSYM(PC_TEMPSAVE, offsetof(struct pcpu, pc_tempsave)) ASSYM(PC_DISISAVE, offsetof(struct pcpu, pc_disisave)); ASSYM(PC_DBSAVE, offsetof(struct pcpu, pc_dbsave)); ASSYM(PC_RESTORE, offsetof(struct pcpu, pc_restore)); +ASSYM(PC_FLAGS, offsetof(struct pcpu, pc_flags)); #if defined(BOOKE) ASSYM(PC_BOOKE_CRITSAVE, offsetof(struct pcpu, pc_booke.critsave)); @@ -106,6 +107,7 @@ ASSYM(TLBSAVE_BOOKE_R31, TLBSAVE_BOOKE_R31*sizeof(regi ASSYM(MTX_LOCK, offsetof(struct mtx, mtx_lock)); +ASSYM(PC_FLAG_NOSRS, PC_FLAG_NOSRS); #if defined(AIM) ASSYM(USER_ADDR, USER_ADDR); #ifdef __powerpc64__ Modified: head/sys/powerpc/powerpc/mp_machdep.c ============================================================================== --- head/sys/powerpc/powerpc/mp_machdep.c Sat Jun 6 02:28:21 2020 (r361858) +++ head/sys/powerpc/powerpc/mp_machdep.c Sat Jun 6 02:40:52 2020 (r361859) @@ -246,6 +246,7 @@ cpu_mp_unleash(void *dummy) printf("Waking up CPU %d (dev=%x)\n", pc->pc_cpuid, (int)pc->pc_hwref); + pc->pc_flags = PCPU_GET(flags); /* Copy cached CPU flags */ ret = platform_smp_start_cpu(pc); if (ret == 0) { timeout = 2000; /* wait 2sec for the AP */